Thanks for the video! How does the command change when the flop is driving a port and the port goes into a flop with a different clock (assume clk_y which is a div/4 version of clk_m)? Will the command now be: set_output_delay 4.2 -clock clk_s [get_ports y]? What about the impact of the clock period at the destination?
Thank you sir for your great explanation. Actually I have few doubts Is it mandatory to set the adding of input delay and output delay is 100% like 70% ,30% of time period of clock period. My clock period is 2ns. And When i am doing synthesis area of the design is changing with respect to input delay and output delays. I am increasing input delay area is also increasing and if decreasing area getting decreasing. how can we choose the delay values of input and output delay? where we will get these values. Could you please help with this sir?
Sir I have a two job roles 1. Synthesis and STA engineer 2. Physical design engineer Which job role is better for work challenge, paysacle and future opportunities?
sir good explanation i had small doubt why the min and max values are not equal as you mention in video that the values signifies we asumes clk-q delay + comb delay for both setup and hold it should be same right (i.e clk-q delay + comb delay) why different values is my doubt
How to know that when clock is reaching to other flops. lets say input side block. If time of clock is 10ns, and your calculated slack is 5.5 but on the other side if clcok reach to input side of flop at 6ns then 6+4.5 will be 10.5 and setup viloation happen.
Thanks a lot for the effort. Please keep explaining. Can you please clarify my doubt. How can we validate "hold violation" on output port paths as Hold window of target flop is not known?
In my design I noticed Set_input_delay 1000 -clock x -clock_fall -fall -max -add_delay [get_port y] Set_input_delay 1000 -clock x -clock_fall -rise -max -add_delay [get_port y] So what's is the significance of fall and max here
Very Good explanation, I have very basic query. How we decide to write , max delay 3.4 and min delay 1.5. why did not choose max delay as 3.3 or 3.5.. Similarly for Min delay 1.3 or 1.6 as min delay . How do you choose or how do you set these values
Nice information....Please can you elaborate on how to calculate/choose the input delay and output delay (like u have taken input delay =3.4ps, how u got this value? and same for output delay (max/min) too?
Thanks for the video!
How does the command change when the flop is driving a port and the port goes into a flop with a different clock (assume clk_y which is a div/4 version of clk_m)?
Will the command now be:
set_output_delay 4.2 -clock clk_s [get_ports y]?
What about the impact of the clock period at the destination?
Very informative thank u
Thank you sir for your great explanation.
Actually I have few doubts Is it mandatory to set the adding of input delay and output delay is 100% like 70% ,30% of time period of clock period.
My clock period is 2ns.
And When i am doing synthesis area of the design is changing with respect to input delay and output delays. I am increasing input delay area is also increasing and if decreasing area getting decreasing.
how can we choose the delay values of input and output delay? where we will get these values. Could you please help with this sir?
Do we need to add clock_latency for input_delay and output_delay?
Sir I have a two job roles
1. Synthesis and STA engineer
2. Physical design engineer
Which job role is better for work challenge, paysacle and future opportunities?
What did you find out? Please let us know
Nice explanation, thank you brother
Thanks
The way of explanation is so good. Can you upload how we can reduce the latency and what are the possible techniques?
ok
Thanks
Very nicely Explained.
Good work.
Thanks
sir good explanation i had small doubt why the min and max values are not equal as you mention in video that the values signifies we asumes clk-q delay + comb delay for both setup and hold it should be same right (i.e clk-q delay + comb delay) why different values is my doubt
How to know that when clock is reaching to other flops. lets say input side block. If time of clock is 10ns, and your calculated slack is 5.5 but on the other side if clcok reach to input side of flop at 6ns then 6+4.5 will be 10.5 and setup viloation happen.
Excellent💯👍
Thanks a lot for the effort. Please keep explaining. Can you please clarify my doubt. How can we validate "hold violation" on output port paths as Hold window of target flop is not known?
hold is calculated at launched flop
In my design I noticed
Set_input_delay 1000 -clock x -clock_fall -fall -max -add_delay [get_port y]
Set_input_delay 1000 -clock x -clock_fall -rise -max -add_delay [get_port y]
So what's is the significance of fall and max here
added rise and fall delay of the input signal they add in the constrains .
Very Good explanation,
I have very basic query. How we decide to write , max delay 3.4 and min delay 1.5.
why did not choose max delay as 3.3 or 3.5.. Similarly for Min delay 1.3 or 1.6 as min delay .
How do you choose or how do you set these values
Bro i this case slack is (-) how it will over come
Nice information....Please can you elaborate on how to calculate/choose the input delay and output delay (like u have taken input delay =3.4ps, how u got this value? and same for output delay (max/min) too?
Sure
What is the difference between set_input_delay vs set_max_delay?
Set max dealy used for asynchronous signals... set input delay i have explained in the vedio
sir, your explanation is good and could you please explain how many constraints used in synthesis stage ?
20-30
Nice explanation sir
thank you
I'm not understanding min delay . Please clear my doubt...
Min delay used for hold , max delay used for setup caluculations
Bro we want same explanation for hold
So much confusion while doing it
amazing
thank you
Sir please make video on FIFO verilog code ,design and interview question related to fifo
Sure i will upload the fifo related topic soon
Please explain min and max delay explain input side with example...bayya
Ok