The Xilinx templates are so useful. You can also use the Xilinx constraint wizard to help as well.
2 роки тому+1
A great intro for anyone new to timing constraints, thank you for making this. At 2:24 you advise to increase the output delay to account for trace length -- But if the clock is sent out from the FPGA, is accounting for trace delays really necessary on the output? After all, the trace delays for the entire communication bus (clock included) is the sam
Thank you very much for this very informative video! I have a question: In this example, the clock came from outside the FPGA, but how do we create a new clock constraint corresponding to the output of a PLL(Clock wizard), and how do we then set delay constraints between some input data and this new internal clock generated by the clock wizard ? I tried using get_ports but it says no ports matched .
Very good explanation. Your github template is missing the set_input_delay calls. As others have mentioned some other examples would be good to cover some other common components that people would need to constrain. Examples I can think of are SDR SDRAM (quite common on cheaper dev boards and usually driven by soft IP unlike DDR), an advanced/counter intuitive example might be asynchronous SRAM where you don't have a true external clock but you can still constrain the interface.
What is the clock frequency in your example? Does the clock period to be higher than the input delay? If the delay is higher than the clock period how this shall be handled?
Hi Stacy, thanks for posting this useful video ! BTW the link to altera paper on timing concepts is not downloadable. Pls put a link where we can download it, or the complete title of the paper. thanks !
Hi, Stacey, Thank you for your amazing videos. I have a simple question about dealing with huge number of input ports... I'm designing a module with 128 * 6 input ports. Is there any way to efficiently code it in a group?? Thanks cheul woo park!!😀😀
Hi Stacey, I recently started following your channel. Thanks for sharing your FPGA/HDL knowledge. Can you please make a more elaborate video on this topic with more examples? Also, the github link(for input_output_timing.xdc) you shared is not accessible. Can you please check? Thanks, Varun
So would you use similar constraints (the 1 nanosecond delay) when interfacing with things like Digilent PMODs? Or are are those slow enough that you don’t worry about it
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It's not so easy to find this kind of content in UA-cam. Thanks for sharing your knowledge!
Glad it was helpful!
The Xilinx templates are so useful. You can also use the Xilinx constraint wizard to help as well.
A great intro for anyone new to timing constraints, thank you for making this.
At 2:24 you advise to increase the output delay to account for trace length -- But if the clock is sent out from the FPGA, is accounting for trace delays really necessary on the output? After all, the trace delays for the entire communication bus (clock included) is the sam
Thank you very much for this very informative video! I have a question: In this example, the clock came from outside the FPGA, but how do we create a new clock constraint corresponding to the output of a PLL(Clock wizard), and how do we then set delay constraints between some input data and this new internal clock generated by the clock wizard ? I tried using get_ports but it says no ports matched .
Very good explanation. Your github template is missing the set_input_delay calls. As others have mentioned some other examples would be good to cover some other common components that people would need to constrain. Examples I can think of are SDR SDRAM (quite common on cheaper dev boards and usually driven by soft IP unlike DDR), an advanced/counter intuitive example might be asynchronous SRAM where you don't have a true external clock but you can still constrain the interface.
What is the clock frequency in your example? Does the clock period to be higher than the input delay? If the delay is higher than the clock period how this shall be handled?
Hi Stacy, thanks for posting this useful video ! BTW the link to altera paper on timing concepts is not downloadable. Pls put a link where we can download it, or the complete title of the paper. thanks !
Thank you for useful video !! ^^
is there any tutorial or any document on how to learn to write the constraint file
Hi, Stacey,
Thank you for your amazing videos. I have a simple question about dealing with huge number of input ports...
I'm designing a module with 128 * 6 input ports. Is there any way to efficiently code it in a group??
Thanks
cheul woo park!!😀😀
Hi Stacey,
I recently started following your channel. Thanks for sharing your FPGA/HDL knowledge.
Can you please make a more elaborate video on this topic with more examples?
Also, the github link(for input_output_timing.xdc) you shared is not accessible. Can you please check?
Thanks,
Varun
+1
Fixed the link! Thanks! I'll definitely do more examples in another video.
@@FPGAsforBeginners Thanks! Looking forward to more videos.
So would you use similar constraints (the 1 nanosecond delay) when interfacing with things like Digilent PMODs? Or are are those slow enough that you don’t worry about it
I'm not 100% familiar with the PMOD but 1ns delay should be fine. If they're slow and nearby then 1ns should be ample.