see , set_clock_groups -asynchronous and fath_path command might be two different commands in the .tcl file , but what end operation the both does is the same , it ignores the timing relationships in the specified path .
Sir , how r u , as u said if there is latch in between two flop then we need to inform the tool for not to do calculations of Timing because it will be false path . I think latch have defined delay so above concept only for Combo latch which has infinite delay then only come in false path ryt?
For half cycle path, hold edge will move to last edge, Even though hold will not violate, but hold equation will have dependency over frequency when we consider half cycle path.... Am I right sir ?
In 3rd point , you are telling that we need to apply set false path if input is coming from other block.... can we apply set input delay and set output delay ...... so which one we have to use?
today only, i saw your video. So informative. Thank you very much sir
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your videos are saviour for me, Thank you sir
Thanks
Hi, what you have explained at 1st point for that path we can assign set_clock_groups -asynchronous also right ?? Please clear my doubt
see , set_clock_groups -asynchronous and fath_path command might be two different commands in the .tcl file , but what end operation the both does is the same , it ignores the timing relationships in the specified path .
This is useful for understanding of flase path
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Nice sir
Superb explanation
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Tqsm sir
Keep doing sir....in future your channel will be like reference for all
So nice of you
Nice explaination sir!
Keep watching
In 3rd example... we do set input delay right?
Set input delay concepts will not come in false path
why we consider the clock path for fix the voilations?
Sir , how r u , as u said if there is latch in between two flop then we need to inform the tool for not to do calculations of Timing because it will be false path . I think latch have defined delay so above concept only for Combo latch which has infinite delay then only come in false path ryt?
yes Sumit.
Hii sir....
How we will get to know false paths and Multi cycle paths are present in our design , by using any command...
Command will not say that ... designer know about false and multi cycle path
For half cycle path, hold edge will move to last edge, Even though hold will not violate, but hold equation will have dependency over frequency when we consider half cycle path.... Am I right sir ?
Hold not depend on frequency
Sir please explain
Having numerical problems in setup ,hold,skew etc
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ok. i will be back
In 3rd point , you are telling that we need to apply set false path if input is coming from other block.... can we apply set input delay and set output delay ...... so which one we have to use?
set input delay constrains we have to use write w.r.t clock right. which clock you will use to write the constraint .