What is the difference between latch and flip flop? When we use level triggering in the given circuit it will act as a latch, while if we use edge triggering by using a clock pulse to the circuit it will function as a flip flop. The latch is functional only when the signal is enabled, while the flip flop function when there is a transition b/w high to low or low to high in the clock pulse signal.
you're too good.... no confusions or flaws unlike the rest of the tutorials.... don't know how to thank you for the your effort you put together in making us comprehend. thanks again :-)
I thought in an SR latch when the inputs S and R (S* and R* in the case of the circuit you drew) were both 1, that the outputs Q and Qnot were invalid, or unknown. At 3:50 you seem to indicate that when S and R are both 1 the outputs are memory (or in other words they retain the same value). I thought that the case when S and R are both 0 was when the outputs were memory.
Thumbs Up ! U guys are Awesome i have easily understood all the concepts you have been taught, your all videos related to multiplexer etc, are easily understandable. I completely appreciates your work ! No doubts and no questions at all! Great work man , keep going !(y) Thank your Very much
I prefer a latch made with one input of a OR gate as the latch Set input. The OR gate output is connected to the input of a AND gate. The other input of the AND gate is connected to the output of an inverter. The inverter input is the Reset input of the Latch. The AND gate output is the Latch output and it is connected to the other input of the OR gate. My understanding is that some integrated circuit outputs can not be connected together without measures being taken to prevent damage. I call the latch circuit above a reset master since a high reset input always results in a low output. To avoid confusion figure any part of the circuit that has a high output is in some way connected to that gates or inverters power supply positive connection. To be honest I have not even tested the above circuit but have tested its relay logic equivalent (which is slightly different).
sir, at 4:43 you said that the circuit will only respond to the edge of the clock...but how does the circuit know that is should respond only at the edge because even in this case the output will change during the high period of the clock pulse.
Latch is anyway part of flip flop, the basic storage element is latch only. The difference is in the controlling, latch is controlled by enable whereas flip flop is by clock.
@@PickledDragon why soo salty? getting a degree in btech isnt that simple it requires hardwork. If they get a job or not after that is none of your buisness. Stop being soo negative towards your own people shame.
None of the bitches understand my point. There are fucking WAY too many BTech bolders in the country. How many of them can articulate what they gobbled up during the course? Do you know what most of them end up doing finally? Go figure it out. BTech is nowadays like 10th grade in the 80s. Everyone has it.
We say Latch/Flip flops are one bit storage circuits,but in truth table,these circuits have two outputs ,one is complement of other.Thus they can store two bits ,then why we call them one bit storing circuits.Sorry if my basics are wrong,i am new to it :)
I sort of see it in this way,let me know if i am right.We never know the data we would want to work upon ,thus we use only one bit from flip flop or latch ckt,as we might know that next bit to be generated is its complement or not.If we use it another way we will have to install a mechanism to check whether we require the complement bit in our data or not,this will add to architecture and efficiency as flip flops will remain same in number and checking mechanism would just extra to the whole circuit thus decreasing efficiency.
It's no longer random once the clock is connected, the clock allows us to know when the circuit is functioning unlike before when it was totally random. As in now we know that the circuit is only operational when the clock signal is transitioning from high to low or from low to high.
I am confused about that part where you are explaining the circuit being a Latch. You said that if the control input is enabled and if EN =0 then S* =1 and R* =1, this is what you called memory. However I thought if those inputs are both equal to 1, that this is an invalid state? Also you never defined what R* is equal to, is R* = R-complement + En-complement?
see the prvs video on SR latch if it done using nor gate then 00 is memory and 11 is invalid if it is done using nand then 11 is memory here they are using nand so 11 is memory.
A flip flop is combination of latches in simple terms. There are other types as well but a positive edge triggered flip flop is a negative level latch connected to a positive level latch. This is some weird explanation. He is clearly confused.
His explanation works well for something like finding the difference between a 74HC373 and 74HC374. Everything has a lower order level of operation that can make higher level functions appear wrong in certain contexts.
Won't the flip flop as enabled by the clock at 5:05 be functional only when the clock is high? Like I don't get why is it edge-triggered/edge-sensitive in this particular design. Even with a clock, the circuit should remain functional only when the level is high, and not just during transition. Am I right? 🙁🙁🙁🙁
Yaa that's a mistake, in this case the circuit is working for En=0. That means you can say that in this case Enable is an Active low signal.(That is just put a NOT gate in front of Enable signal and now the circuit will work whenever it is high)
Actually it is correct, if you notice when you take ebable = 0, it will make both S* and R* = 1 that is the memory state. And if you take enable= 1 it will give S*=S complement and R*= R complement, which is a valid operable condition for the latch. Even though you asked this question 3 years ago, there might be people like me reading the comments 😂. Hope this helps. Peace
sir! after explaining Enable : s* = E+(S-bar).. why did you use ( + ) here however the gate is NAND , not OR .. can you explain it to me .. Thank you ..
+photoyork : Bcuz if E = 0 then E' = 1 & according to this eqn : E' + S' , feed in the value of E' as 1 !! Then acdng to De Morgan's thm, (1 + Anything = 1 Only) , hence S* = 1 !!
I am confused on the part where you said that the ckt is only operational when En is high, but then you show that it works when En is 0. Does this mean that the ckt only works when En is 0?
i have a doubt ... lets consider edge triggering ....so you said that the curcuit will be active only when the signal makes a transition from low state to high state or vice versa.........so what happens to the circuit during high and low stages
@@Skipdiskcheck haha quite true! But, imagine the satisfaction and nostalgia of coming back to this video, and if incase he hadn't got his doubt cleared, finally cleared!
A clock(clk) is a pulse that happens at a certain frequency. This is the frequency the system works at. (The clk is continually sending pulses.) Every time the clk pulse enters the flip-flop it is able to change state depending on the input values. While the enable is a signal that enables the flip-flop to either register an input or not. If enable is 0, the output will always be 0. If the enable is 1 then the output depends on the input. The enable has no frequency and can be chosen by the user, or machine. While the clk is always running and sending pulses.
Enable signal is different from clock. It isn't regular like clock which suggests that it is generated by some other logic. The device will work as long as the enable is positive. On the other hands, clocks are regular and the flip flop works on the edge triggering of clocks.
@@thakermahek2501 Because those are the definitions. I had the same question. My perception is that simple flip-flops and latches behave similarly in simple circuits, but differ in behaviour when circuits implement both edge-triggered and level synchronising.
3:21 You said "If the value of En = 1, this means that S* is S' ". How come? S* depends on En and S. So, just by knowing En, we can't predict the value of S*.
sir, if clock is what is concerned for determining flip flop or latch why is the circuit for latch operational for en =0 in case of latch as it should have been en=1 as per your words
When enable is zero, the Q and Q' won't change. It simply means that we don't wanna change the Q and Q' until we need to update. It doesn't mean that the device stopped working. When enable is one, the Q and Q' change the state based on R and S values. I know it's too late. But wanted to reply just for my reference. 😂😂😂
how output will change in positive edge triggering flipflop when it goes from lower to higher state (0 to 1). why output will not change in positive edge triggering flipflop when it remains in higher state(1)? , as the flipflop will be active when its clock input or enable input is in higher state(1).
In that circuit when you show the difference between latch and flip flop i don't understand why did you used nand gate in front of the clock wire ( when the clock is high or on after the nand gate it should be off and i don't want that right ).
please help regarding this, it is wrong in video, caus it means in case of enable equals to 1, its not latching, its rather transitioning in different according to S and R value, so when enable is 0 then only it will be S and R latch, so in the lecture he was telling when enable is 1 then it will be working is latch,
What is the difference between latch and flip flop?
When we use level triggering in the given circuit it will act as a latch, while if we use edge triggering by using a clock pulse to the circuit it will function as a flip flop.
The latch is functional only when the signal is enabled, while the flip flop function when there is a transition b/w high to low or low to high in the clock pulse signal.
the sound track used at the beginning of this channel's videos is "Be Thankful" by Shannon Kaiser and Kevin MacLeod, if at all some one cares btw.
Yes. Some people do care.
thanks I love that music and i wanted full track.. thanks a lot
I did not get this track ;(
@@kishor-jena me too😂
@@adarshsasidharan254 😁
PLEASE MAKE VIDEOS ON DIGITAL LOGIC FAMILIES (TTL, ECL, CMOS etc) and ADC and DAC conversions.
Your lectures are great.
Thank you so much for them.
you're too good.... no confusions or flaws unlike the rest of the tutorials.... don't know how to thank you for the your effort you put together in making us comprehend. thanks again :-)
I can listen to Neso Academy in my sleep and still learn something. Thank you!
Ye Kuch zyada nahe hogya bhai Saab hhh
Sir, my request is to add lecture no. in title of the lecture.
its on photo displayed before playing video
Sir please do that. Because even if UA-cam does not suggest the video, we can search
@@NikhilKumar-pf2toyou mean thumbnail
@@debo9191😄🐥🐣
I thought in an SR latch when the inputs S and R (S* and R* in the case of the circuit you drew) were both 1, that the outputs Q and Qnot were invalid, or unknown.
At 3:50 you seem to indicate that when S and R are both 1 the outputs are memory (or in other words they retain the same value).
I thought that the case when S and R are both 0 was when the outputs were memory.
***** Thank you very much for your response, I did not realize my error.
These videos are great and I have learned a lot from them.
dude i had the exact same question you are amazing
1
can you please explain the ans of this que to me !
@@ishan9209 This is NAND SR latch, when both S & R are 1 then it acts as memory.
Hope you get it!
We are using the NAND gate but the eq you write for Q* and for S*is the eq for NOR gate
Plz consider it
Yes
yeah, he must have goofed
NAND gate is NOT(A AND B) and by DeMorgan's Law it turns to NOT(A) OR NOT(B) so technically the video is correct I think?
@@danischn6246 Thanks for the explanation of it, I think that's what is used here I was quite confused as well when that expression came up haha
@@danischn6246 that makes so much sense ty
Thanks a lot sir , the lectures are greatly helpful.
Difference between LATCH & FLIP FLOPS :
Latches are level triggered while flip flops are edge triggered.
Wow! U r awesome! Please explain Mechanics and Thermodynamics. Plss!!
that wud be so gr8
😂
Appki video mai apne lecture ko dikhya we bahut satisfy hue apki video se.
Subscribe bhi kiye hai.
1 MILLION SUBSCRIBERS COMING SOON😁
Thumbs Up ! U guys are Awesome i have easily understood all the concepts you have been taught, your all videos related to multiplexer etc, are easily understandable. I completely appreciates your work ! No doubts and no questions at all! Great work man , keep going !(y) Thank your Very much
I prefer a latch made with one input of a OR gate as the latch Set input. The OR gate output is connected to the input of a AND gate. The other input of the AND gate is connected to the output of an inverter. The inverter input is the Reset input of the Latch. The AND gate output is the Latch output and it is connected to the other input of the OR gate. My understanding is that some integrated circuit outputs can not be connected together without measures being taken to prevent damage. I call the latch circuit above a reset master since a high reset input always results in a low output. To avoid confusion figure any part of the circuit that has a high output is in some way connected to that gates or inverters power supply positive connection. To be honest I have not even tested the above circuit but have tested its relay logic equivalent (which is slightly different).
What would happen if we were to use NOR gates for the S and R part (gates drawn in yellow) instead of NAND gates?
sir, at 4:43 you said that the circuit will only respond to the edge of the clock...but how does the circuit know that is should respond only at the edge because even in this case the output will change during the high period of the clock pulse.
The way he writes directly S* = S'+En', is like we are familiar with De-morgan from nursery or kindergarten 😅👶
best channel on yt.
बहुत मस्त समझाते हो आप।।
धन्यवाद
Sir . I dont know how to thank u. But ....... increadible effort
sir due to your lectures I pass the B.Tech . Thank You Sir
same here..haha
which college??
Latch is anyway part of flip flop, the basic storage element is latch only. The difference is in the controlling, latch is controlled by enable whereas flip flop is by clock.
@@PickledDragon why soo salty? getting a degree in btech isnt that simple it requires hardwork. If they get a job or not after that is none of your buisness. Stop being soo negative towards your own people shame.
@@PickledDragon onnu podo
None of the bitches understand my point. There are fucking WAY too many BTech bolders in the country. How many of them can articulate what they gobbled up during the course? Do you know what most of them end up doing finally? Go figure it out. BTech is nowadays like 10th grade in the 80s. Everyone has it.
Thank you so much sir, you are helping a lot by your videos. We all are beneficial with your videos.
Keep going sir, we all supports you.
Thank you.
We say Latch/Flip flops are one bit storage circuits,but in truth table,these circuits have two outputs ,one is complement of other.Thus they can store two bits ,then why we call them one bit storing circuits.Sorry if my basics are wrong,i am new to it :)
I sort of see it in this way,let me know if i am right.We never know the data we would want to work upon ,thus we use only one bit from flip flop or latch ckt,as we might know that next bit to be generated is its complement or not.If we use it another way we will have to install a mechanism to check whether we require the complement bit in our data or not,this will add to architecture and efficiency as flip flops will remain same in number and checking mechanism would just extra to the whole circuit thus decreasing efficiency.
can you store 1 & 1 at the same time?
Sir please do videos on logic families...and memories
@3:12 Nand Gate op= ~S* and ~En* Its Not NOR gate.
Audience
Output of NAND gate,
S*=(S.En)’
You can convert it into another form using De Morgan’s law
S*=S’+En’
Latches are level triggered and Flipflops are edge triggered.
Thank you sir, it was worth watching this video..
Wow.. you made something so easy--so complicated.
Sir, please upload videos on logic families
the lecture are greatly helpful thanks a lot
Sir,does clk mean it has only 50% duty cycle?if yes then can flipflop work with a random pulse?
It's no longer random once the clock is connected, the clock allows us to know when the circuit is functioning unlike before when it was totally random. As in now we know that the circuit is only operational when the clock signal is transitioning from high to low or from low to high.
Question at 3:53 Why is S* = 1 and R* =1 => memory? Shouldn't that create an invalid condition?
well explained sir!
why you said that latch works whenever enable is high whereas it is storing memory when enable is low?
Same question is mine also
No it is not storing when enable is low, as there is NO OUTPUT
Thank you for posting !
Nand SR latch is in memory mode when set and reset are all 1.This is diffierent from the Nor SR latch.
Thank you! very clear and impressive!!
I am confused about that part where you are explaining the circuit being a Latch. You said that if the control input is enabled and if EN =0 then S* =1 and R* =1, this is what you called memory. However I thought if those inputs are both equal to 1, that this is an invalid state? Also you never defined what R* is equal to, is R* = R-complement + En-complement?
see the prvs video on SR latch if it done using nor gate then 00 is memory and 11 is invalid if it is done using nand then 11 is memory here they are using nand so 11 is memory.
@@dhanyabhatk3608 why would the circuit/latch not work when it is memory? it will not work when in not used state
At 3:21 how you are using or gate formula
Apply De'Morgan's theorem to nand gate. Then u will get this.
why we are using NAND gate and formulating the expression with OR operation??
it is the expression of NAND gate after using demorgan's theorem
a.b whole bar gives a bar plus b bar
Very good presentation H/w option B
A flip flop is combination of latches in simple terms. There are other types as well but a positive edge triggered flip flop is a negative level latch connected to a positive level latch. This is some weird explanation. He is clearly confused.
His explanation works well for something like finding the difference between a 74HC373 and 74HC374.
Everything has a lower order level of operation that can make higher level functions appear wrong in certain contexts.
Won't the flip flop as enabled by the clock at 5:05 be functional only when the clock is high? Like I don't get why is it edge-triggered/edge-sensitive in this particular design. Even with a clock, the circuit should remain functional only when the level is high, and not just during transition. Am I right?
🙁🙁🙁🙁
Thank you very much sir🥳🥳🥳🥳
Wow you wrecked my university teacher in 5 minutes 32 seconds. Thank you so much, i finally learned this.
Thank you soo much sir , very clear explanation
Thanks for the video series! You saved my ass, my prof is terrible!
Nice clarification
Q and Q inventory are the memory outputs but u are saying that S* And R* are memory and it is equal to the case 3
Very nice lecture...
You said that whenever enable is high then only ckt will work.
but in the above video ckt is working when en=0.
I am not getting this.
Yaa that's a mistake, in this case the circuit is working for En=0. That means you can say that in this case Enable is an Active low signal.(That is just put a NOT gate in front of Enable signal and now the circuit will work whenever it is high)
He should use AND gate for clk instead NAND
Actually it is correct, if you notice when you take ebable = 0, it will make both S* and R* = 1 that is the memory state. And if you take enable= 1 it will give S*=S complement and R*= R complement, which is a valid operable condition for the latch.
Even though you asked this question 3 years ago, there might be people like me reading the comments 😂.
Hope this helps.
Peace
@@adarshsasidharan254 yup!
ur comment helped me today just hours before my semester exam...😂😂😂
@@bhavsagar5 😂 I'm glad my exams are over
sir!
after explaining Enable :
s* = E+(S-bar)..
why did you use ( + ) here
however the gate is NAND , not OR ..
can you explain it to me ..
Thank you ..
here s* = (e.s)' = e' + s'
+photoyork : Bcuz if E = 0 then E' = 1 &
according to this eqn : E' + S' ,
feed in the value of E' as 1 !!
Then acdng to De Morgan's thm, (1 + Anything = 1 Only) ,
hence S* = 1 !!
no see 3:39 ,S*=1 when en'=1
Monima Chowdhury ohh ya thnx mam
There is a rule that says (AB)' =(A'+B')
🤟🤟🤟🔥🔥🔥 aage badte raho
nice explanation
I am confused on the part where you said that the ckt is only operational when En is high, but then you show that it works when En is 0. Does this mean that the ckt only works when En is 0?
That what I called quality 👏
Finally I get it, thank you
please upload digital communication lessons sir
thanks
very very very nice👏👏👏👏
i have a doubt ... lets consider edge triggering ....so you said that the curcuit will be active only when the signal makes a transition from low state to high state or vice versa.........so what happens to the circuit during high and low stages
Nothing happens because it only is triggered at the edge or the rising or falling phase only, not the high and low levels or stages.
@half-soul8393 bruh....its high time he might have completed his graduation and might have got a job by now🙂
@@Skipdiskcheck haha quite true!
But, imagine the satisfaction and nostalgia of coming back to this video, and if incase he hadn't got his doubt cleared, finally cleared!
Hi , I think you have done mistake by saying that S*=S(inverse)+En(inverse) , it should be S*=S(inverse)*En(inverse)
There is no mistake, please check the circuit.
apply boolean law - (AB) complement = A comp + B complement
Apply de Morgan's Law after that
Thnks for your guidance. May ALLAH bless you.
please add floating point representation videos
Thank You
Sir,
Which reference book you used for this topic .....Tell me because in some books there are different circuit of latch and it's explanation
WELL DONE
what is the difference between Enable and clock?
A clock(clk) is a pulse that happens at a certain frequency. This is the frequency the system works at. (The clk is continually sending pulses.) Every time the clk pulse enters the flip-flop it is able to change state depending on the input values.
While the enable is a signal that enables the flip-flop to either register an input or not. If enable is 0, the output will always be 0. If the enable is 1 then the output depends on the input. The enable has no frequency and can be chosen by the user, or machine. While the clk is always running and sending pulses.
Then what about enable?
Enable signal is different from clock. It isn't regular like clock which suggests that it is generated by some other logic. The device will work as long as the enable is positive. On the other hands, clocks are regular and the flip flop works on the edge triggering of clocks.
Awesome sir
Thank u sooooo much sir .😊
Why we didn't use three input nand gate to control inputs ...I mean to add clock to ckt...??
i dnt get it. why cant the circuit be used as a flipflop while keeping the clock as level triggered?
Yes... Same question
@@thakermahek2501 Because those are the definitions. I had the same question. My perception is that simple flip-flops and latches behave similarly in simple circuits, but differ in behaviour when circuits implement both edge-triggered and level synchronising.
Sir, is in rectangular signal or duty cycle is not 50 percent, if edge triggering is apply then, it is flip-flop or latch?
3:21 You said "If the value of En = 1, this means that S* is S' ". How come?
S* depends on En and S. So, just by knowing En, we can't predict the value of S*.
Thanks
sir, if clock is what is concerned for determining flip flop or latch why is the circuit for latch operational for en =0 in case of latch as it should have been en=1 as per your words
When enable is zero, the Q and Q' won't change. It simply means that we don't wanna change the Q and Q' until we need to update. It doesn't mean that the device stopped working. When enable is one, the Q and Q' change the state based on R and S values.
I know it's too late. But wanted to reply just for my reference. 😂😂😂
when we apply clock for flip flops what is the input send to the nand gate while leading edge/falling edge case?
sir. excuse me ,the the gate that obtain s* is NAND there for S*='s.en or i am wrong
expand it using De Morgans you will get the same
It's S* = (S . En)' = S' + En'
So it's like that
how output will change in positive edge triggering flipflop when it goes from lower to higher state (0 to 1).
why output will not change in positive edge triggering flipflop when it remains in higher state(1)? , as the flipflop will be active when its clock input or enable input is in higher state(1).
Superb
Sir make a clear video on active low and active high enable input
Someone is calling you 2:32 😅😅
please make video on ..linear integrated circuit opamp and ...ce cc cb amplifier
Superb explanation.
thank you sir
In that circuit when you show the difference between latch and flip flop i don't understand why did you used nand gate in front of the clock wire ( when the clock is high or on after the nand gate it should be off and i don't want that right ).
what is the maximum frequency can be given to a flip flop ?
Well understanding...
But in the book, it's given that if En = 0, there is a don't care for S and R, and no change occurs. Here S and R acts as selection lines
thank you ....nice present
which flip flop or latch circuits we use in servers . I am asking because in server we have to use flip flop without delay .
sir please upload lessons on digital communication and also tutorial problems in digital communications
sir is there any other difference between flip-flop and latches
This is really amazing😍
Isn't it the same as a level-triggered flip flop? Why did you say that it will act as a flip flop only under edge triggering?
please help regarding this, it is wrong in video, caus it means in case of enable equals to 1, its not latching, its rather transitioning in different according to S and R value, so when enable is 0 then only it will be S and R latch, so in the lecture he was telling when enable is 1 then it will be working is latch,
exactly i had the same doubt
What is operational and functionsl in given lecture ???
Good video
Great! Thanks again.