What my lecturer could not make me understand easily, i just got the easiest lecturer that has made understood 100% for free. I'm grateful for this channel
I deeply appreciate that even this far into the lectures, you still go over the basic things like the k-maps instead of just assuming the viewer knows how to do it. It helps so much with conceptualization and I see almost nobody doing it, so thank you a ton.
This is one of the best UA-cam channels for studying digital electronics. It clears all my concepts and makes learning so easy. Good going Neso Academy!
You are actually working towards making our country developed by developing 1. the brains of so many students in digital electronics who cannot easily understand the concepts 2. mainly free of cost!. THANK YOU SIR.
Thanks to you, sir, I have cleared my internal examinations of Digital Electronics. Thank you very much. Shout out to Neso Academy! Keep up the good work.
I love you! Sir, you've managed to explain everything in such a simple and clear way, I'm so so grateful! Whatever takes my uni professor an hour to analyze (and confuse us even more), can be found in a ten minute video of yours. I vow to thee!!
Hello everyone :) i believe i how found the explanation to the confusion we are all sitting with. How do we get 0 and 1 as Qn in the truth table's two middle cases.? First, what we must understand is that Qn represents the value of Q in a Nand-SR flip flop. (Q bar) is not represented in this truth table example as it is not relevant in some sence. Next, we must for ourselves try to visualize the Q output. First, let's put: Clock = 1, S=0, R=1. through the first nand gate at the top, (in previous lecture) we take 1 and 0 as inputs and get the S* as 1. For clock and R as inputs we get 1,1 which is 0 (according to our nand-gate truth table. so now we have S* as 1 and R* as 0. If we try to remember the SR-latch walkthrough he did a couple of lectures ago, we know that whenever S is 1, then Q is automatically 0, and when putting that input into the bottom nand-gate with R* then we get 1. so now we have S = 0, and R = 1. However, as mentioned just before, Qn represents the Q, not Q complement. So Qn represnets the Q, which is 0. therefore we put the 0 into the truth table as the value of Qn. For the third case where S = 1 and R = 0, (clock is ofcourse 1) Then the top nand-gate resolves into 1*1 = 0 = S*, and the bottom nand-gate resolves into 1*0 = 1 = R*. so whenever Reset is 1, then (Q compliment) is 0. and when you use 0 as an input for the top NAND-gate with S* then you get 1.. Again, it is very important to remember that Qn represents Q in our Sr flip flop truth table in previous lecture, so (Q compliment ) which is 0, is not included. So basically if you sit down, draw out the SR flip flop sequential circuit with control input as clock, and take clock as 1, and try both: S = 0, R = 1 S = 1, R = 0 Then you will get Q as Q = 0, (Q Bar) = 1 Q = 1, (Q Bar) = 0 But Qn again represnets Q, so the answer for case two would be: Case 2: 0 Case 3: 1. I apologize if i said the same words too many times :) but i don't want to loose anyone :) on beforehand :) thank you :)
Thanks a lot for such a good explanation in such simple way.... thumbs up... your way of breaking the long lecture in to smaller pieces is really impressive and understandable..
I have a sequential logic exam today and was looking for that EXACT explanation for hours. The learning materials for sequential logic nets, we got from our professor, listed an excitation table for RS-flipflops and other logic operators. But nobody ever mentioned what an excitation table actually was?! NOWHERE and I repeat NOWHERE on the web could I find an explanation. Even the English Wikipedia article on excitation tables gives an explanation in words as to how one gets to an excitation table that´s about two sentences long. Of course that didn´t help me. THIS is the shit. This is what I was searching for. I could hug and kiss this man. God bless him.
First of all thank you so very much for this fantastic presentation. However I have 1 question left that is still puzzling me: why did you mark the invalid cases as "don't cares"?
it is so simple bro-that is invalid case-thus we can't determine the exact output for that case-but it should be of either 0 or 1-thus sir marked don't care
How did you give the value for Q(n+1) when the values of S and R are 0,1 and 1,0 as 0 And 1?? Thanks in Advance.Your Lectures are very Nice and Helping!!
As this is a NOR SR Flipflop, we know from NOR SR Flipflop truthtable, when clk=1, S=0, R=1, Q=1 So here Q+1= 1+1=0. Similarly incase of NOR SR Flipflop when clk=1, S=1, R=0, Q=0 so here Q+1= 0+1=1. [I guess Q and Qn are same thing, and Q' is neglected]
I just realized that i have wasted money behind varsity .. Belongs full semester i didn't even understand anything but two days before of semester final exam i have completed my full course with the help of your video ..
Hi, Neso. Thank you for your clear and thorough videos. I have just one doubt: why are the invalid states from the characteristic table used as don't cares on the k-map? It's a question some watchers are asking.
Alexandre Soares da Silva Invalid case arises when output can be anything (0 or 1) and is not controlled by inputs. So it is a type of don't care condition only.
Thank you so much first time i understood flip flop properly. I had hard time understanding flip flop throughout my engineering but finally i got everything. Just wanted to know why we made this different tables. What are there uses i have completed all the videos till now may be i will understand this in later videos and if not please answer. Thanks a lot
Hello sir in the previous you have explained sr latch with help of NOR AND NAND GATES there you have used NAND gate of I'm not wrong...and for input 00 you have written NO CHANGE (MEMORY) BUT for NAND GATE it is NOT USED..... You have said that NAND and NOR are opposite .....THANQ....SIR FOR EXPLAINING THE CONCEPTS IN DETAIL.....
sir ,in characteristic table when we put clock=1 then it will become level triggring,not the edge triggring.. so there is n difference btwn clock and enable??? plz answr it
Hi, I really think truth table in this video is actually the characteristic table and the one that is shown as characteristic table is the actual truth table. Please correct me if I am wrong. Thank you :)
we can use the minterm formula to acquire a boolean expression for S and R. S=sum of minterm(1)+ Minterm 3 is a dontcare or we can construct a K map with Qn and Qn+1 , fill in the values for S and where we have dont care put a 1.S=Qn+1. Similarly for R=~Qn+1. If i am wrong someone please correct me!
sir you have made the characteristic table using the truth table of sr nand latch . does the table remain the same when we make it using sr nor latch and if no then how? pls explain
thank you sir sir,why the invalid cases of characteristic table is not considered as don't cares while written excitation table.. but in kmap invalid cases are considered as don't care??
This should be considered a public service. I'm so grateful for the work of this Channel.
Yes, friend he had nicely explained the concepts....
Brother, you explain digital electronics as if you are the one that develop flipflops and latches.
What a great job!
What my lecturer could not make me understand easily, i just got the easiest lecturer that has made understood 100% for free. I'm grateful for this channel
I deeply appreciate that even this far into the lectures, you still go over the basic things like the k-maps instead of just assuming the viewer knows how to do it. It helps so much with conceptualization and I see almost nobody doing it, so thank you a ton.
This is one of the best UA-cam channels for studying digital electronics. It clears all my concepts and makes learning so easy. Good going Neso Academy!
Yes, he had nicely explained the concepts...so you are absolutely right.....
You are actually working towards making our country developed by developing 1. the brains of so many students in digital electronics who cannot easily understand the concepts 2. mainly free of cost!. THANK YOU SIR.
Yes, he had nicely explained the concepts....
Thanks to you, sir, I have cleared my internal examinations of Digital Electronics. Thank you very much. Shout out to Neso Academy! Keep up the good work.
Yes, friend he had nicely explained the concepts....
I love you! Sir, you've managed to explain everything in such a simple and clear way, I'm so so grateful! Whatever takes my uni professor an hour to analyze (and confuse us even more), can be found in a ten minute video of yours. I vow to thee!!
Hello ....??
PLEASE MAKE VIDEOS ON DIGITAL LOGIC FAMILIES (TTL, ECL, CMOS etc) and ADC and DAC conversions.
Your lectures are great.
Thank you so much for them.
Hello everyone :) i believe i how found the explanation to the confusion we are all sitting with.
How do we get 0 and 1 as Qn in the truth table's two middle cases.?
First, what we must understand is that Qn represents the value of Q in a Nand-SR flip flop.
(Q bar) is not represented in this truth table example as it is not relevant in some sence.
Next, we must for ourselves try to visualize the Q output.
First, let's put:
Clock = 1, S=0, R=1.
through the first nand gate at the top, (in previous lecture) we take 1 and 0 as inputs and get the S* as 1.
For clock and R as inputs we get 1,1 which is 0 (according to our nand-gate truth table.
so now we have S* as 1 and R* as 0.
If we try to remember the SR-latch walkthrough he did a couple of lectures ago,
we know that whenever S is 1, then Q is automatically 0, and when putting that input into the bottom nand-gate with R* then we get 1. so now we have S = 0, and R = 1.
However, as mentioned just before, Qn represents the Q, not Q complement.
So Qn represnets the Q, which is 0. therefore we put the 0 into the truth table as the value of Qn.
For the third case where S = 1 and R = 0, (clock is ofcourse 1)
Then the top nand-gate resolves into 1*1 = 0 = S*, and the bottom nand-gate resolves into
1*0 = 1 = R*. so whenever Reset is 1, then (Q compliment) is 0. and when you use 0 as an input for the top NAND-gate with S* then you get 1..
Again, it is very important to remember that Qn represents Q in our Sr flip flop truth table in previous lecture, so (Q compliment ) which is 0, is not included.
So basically if you sit down, draw out the SR flip flop sequential circuit with control input as clock, and take clock as 1, and try both:
S = 0, R = 1
S = 1, R = 0
Then you will get Q as
Q = 0, (Q Bar) = 1
Q = 1, (Q Bar) = 0
But Qn again represnets Q, so the answer for case two would be:
Case 2: 0
Case 3: 1.
I apologize if i said the same words too many times :) but i don't want to loose anyone :)
on beforehand :) thank you :)
thaks dude
Thanks in some words just ignore q bar right,and just compare the 3rd case for not used
so basically Q = Qn
Sir Q is present state but Q(n+1) is next state so how Q=Q(n+1) ?
Thanks Buddy!!
9 years old class still has the best quality ❤
its 2020 ,these lectures were posted 5 years ago, but still help full. may God Bless You.
Check out 2024 - it's still saving lives
Each video so far was above average educational quality.
Concise and right length.
Thx
Absolutely right....
Thank You So much for such a great and simple lecture. It's sequential way of teaching which is very easy to understand.
You a life saver brother you know that right?
Thanks a lot for such a good explanation in such simple way.... thumbs up... your way of breaking the long lecture in to smaller pieces is really impressive and understandable..
I declare u the next recipient for noble prize
Yes, friend he had nicely explained the concepts....
😂 average indians 😂😂😂
😂
I have a sequential logic exam today and was looking for that EXACT explanation for hours. The learning materials for sequential logic nets, we got from our professor, listed an excitation table for RS-flipflops and other logic operators. But nobody ever mentioned what an excitation table actually was?! NOWHERE and I repeat NOWHERE on the web could I find an explanation. Even the English Wikipedia article on excitation tables gives an explanation in words as to how one gets to an excitation table that´s about two sentences long. Of course that didn´t help me.
THIS is the shit. This is what I was searching for. I could hug and kiss this man. God bless him.
Yes really nice explanation......
You are the Leonard for Logic Design subject.
awesome explanation sir...now I am able to draw flipflops and its table on my own...THANK YOU...
Sir the teaching is so so amazing keep goin like this I really enjoyed learning this way thank u so very much it helped my exams 😊🙏
Roll number in username 👁️👄👁️
Dear, don't put your Roll no in your username. Chances of it getting manhandling increases
Explanations are clear, pedagogy is top notch thanks from France =)
Absolutely correct.....
Tomorrrow is my exam! And this helped me alot ... Thanku very much 😋
value of s= Qn+1
value of r = Qn+1 bar ...using 4 cells k map
thankuuu so much.❤..mam ne krwaya tha class me pr mai bhul gyi thi..and u remind me the whole again..thankuu..your explanation is really good😊😊
Yes, friend he had nicely explained the concepts....
Great stuff thank you. If anyone is having issues, look at the previous videos. Does a great job explaining everything
Yes his videos are really helpful
First of all thank you so very much for this fantastic presentation. However I have 1 question left that is still puzzling me: why did you mark the invalid cases as "don't cares"?
same question
it is so simple bro-that is invalid case-thus we can't determine the exact output for that case-but it should be of either 0 or 1-thus sir marked don't care
Really puzzle breaking tutorial for me on these concepts. very nice.
Yes, friend his explanation is really helpful
I guess this charateristics table is When we used NOR gate, right??
as u said when s=r=0 then memory
How did you give the value for Q(n+1) when the values of S and R are 0,1 and 1,0 as 0 And 1?? Thanks in Advance.Your Lectures are very Nice and Helping!!
Yeah that's what I also wanna know !!
@@spacepacehut3265 and did you get it?
@@spacepacehut3265 Same here. If you know kindly tell me too
As this is a NOR SR Flipflop, we know from NOR SR Flipflop truthtable, when clk=1, S=0, R=1, Q=1 So here Q+1= 1+1=0. Similarly incase of NOR SR Flipflop when clk=1, S=1, R=0, Q=0 so here Q+1= 0+1=1.
[I guess Q and Qn are same thing, and Q' is neglected]
Thank you sir for excitation table🙏🙏🙏
I just realized that i have wasted money behind varsity .. Belongs full semester i didn't even understand anything but two days before of semester final exam i have completed my full course with the help of your video ..
Hi, Neso. Thank you for your clear and thorough videos.
I have just one doubt: why are the invalid states from the characteristic table used as don't cares on the k-map? It's a question some watchers are asking.
Alexandre Soares da Silva Invalid case arises when output can be anything (0 or 1) and is not controlled by inputs. So it is a type of don't care condition only.
The prev video actually explained this thing🙂
it didnt actually
@@dasamlan9874
That was very helpful. sir. excellent explanation.
Very nice explanation
Thank you so much bro❤❤❤🎉
Thank you sir 🙏 All videos are very helpful and very well presented 🙏🙏
Best teacher for Digital electronics
Absolutely right....
This chanel not only provides digital electronics but its also provides the best lectures of engineering subjects
Well done👏👏
Neso Academy.. Oh Thank you so much... I understand it very clearly.... Thank you ...
Very clear explanation...
this guy xplain it way simplier 👍🏻👍🏻👍🏻
I am studying every subject form this channel.
thanks alot sir , your lectures are life savor :): ))
good explanation sir. Why do you consider invalid case as don't care?
well explained thank you so much👍👍
Thank you so much first time i understood flip flop properly. I had hard time understanding flip flop throughout my engineering but finally i got everything. Just wanted to know why we made this different tables. What are there uses i have completed all the videos till now may be i will understand this in later videos and if not please answer.
Thanks a lot
Hello Alka, I hope you understood the concept clearly.....
Thanks a lot due to this i can understand very easily
I am watching this video at 1:12 am
and I have my semester exam at 9:00 am. God help me and bless this man
Very helpful. Love you for these tutorials. Thank you
Good presentation 👍...i really got it
Neso is god of digital electronics
nice one !! help me to understand more about this chapter for my final exam...
Thaaaaaaaku so much sir kitta bhi thanks bolu kaam h apke liye to
Yes, really nice video.....
Great teaching ❣️
Thank you sir
Excellent explaination
Thank you
Neso Academy.
Very good explanation so easy to understand thanx for this video👍
Yes really nice videos and nice explanation....
Thank you Neso
Given Rs 50 via UPI , a small contribution for the great service u do , y'all should do same !
do you have any lecture on Analog designs?
Thank you 🛐
Hello sir in the previous you have explained sr latch with help of NOR AND NAND GATES there you have used NAND gate of I'm not wrong...and for input 00 you have written NO CHANGE (MEMORY) BUT for NAND GATE it is NOT USED.....
You have said that NAND and NOR are opposite .....THANQ....SIR FOR EXPLAINING THE CONCEPTS IN DETAIL.....
sir ,in characteristic table when we put clock=1 then it will become level triggring,not the edge triggring..
so there is n difference btwn clock and enable???
plz answr it
Sir, can you please tell me, when S=0 , R=1 & S=1 , R=0 , How did we get the values of Qn+1 as 0 and 1 respectively.
same doubt he skipped that part
Thank you for the lesson.
Thank you so much, you're doing a really instrumental work for students
Yes, friend he had nicely explained the concepts....
great work sir!!!
I truly respect u...!
Hi, I really think truth table in this video is actually the characteristic table and the one that is shown as characteristic table is the actual truth table. Please correct me if I am wrong. Thank you :)
I think so the one in the video is correct
I correct u😂
Thank you so much for such an amazing content I have a doubt that why you use that invalid case as don't care in k-map
Yes, friend his explanation is really helpful
Thank you very much sir🥳🥳🥳🥳
Sir please explain the 3rd and 4th cases of the truth table, I think they should be Qn only not 0 and 1.
very good videos. ...it helped me lot to score good in exams. thanks! !!
+Jaya Sharma Mumbai university???
no
no
*awkward*
Hello sir , you said at the end of lecture ( find value of S and R yourself) what do you mean by it? And how can we find them ? Please help
Thank you, sir.
This should be considered a public service
Why should we consider invalid outputs as don't care conditions while writing the K-map?
Thank You Sir 🙏🤲❤️
really its so clear explanation, you are the best tauter
Thank you
THANK YOU SO MUCH
Thank u so much.. U r an amazing teacher
Super very useful sir
top quality teaching
Exactly....
Thanks Maya ❤️👍
Maya?
OMG! Great lecture.
Yes, friend he had nicely explained the concepts....
how values of Qn+1 come in truth table please explain?
check the present state and input of s and R then value come in truth table
your are the best explainer
Sir, we need lectures on power electronics
I'm watching this at 12:06a.m. because i couldn't understand the class at all. Thank you Indian guy
Yes, friend he had nicely explained the concepts....He is an indian?
Hello sir, you are explaining very well but I just don't the part from k-map 7:10 plz help or suggest something to me. Thank you!
What will be the value of S and R value with the help of K-map and also why the result of the K-map of Qn and SR is Qn +1?
we can use the minterm formula to acquire a boolean expression for S and R. S=sum of minterm(1)+ Minterm 3 is a dontcare or we can construct a K map with Qn and Qn+1 , fill in the values for S and where we have dont care put a 1.S=Qn+1. Similarly for R=~Qn+1. If i am wrong someone please correct me!
thank you so much
sir you have made the characteristic table using the truth table of sr nand latch . does the table remain the same when we make it using sr nor latch and if no then how?
pls explain
Next state concept is really typical....explain it clearly
thank you sir
sir,why the invalid cases of characteristic table is not considered as don't cares while written excitation table.. but in kmap invalid cases are considered as don't care??
Wow its really very very good.....
In the truth table,how value of Q(n+1) become 0,1?Can you please clarify
That's because we find Q or Q(n+1) using set and reset values .
@@sravanikatasani6502 just tell me that....if Q=0 and Q'=1 then why we write 0 as Q(n+1) ??
@@yogeshmourya981 it depends on the inputs s and r. If both are 0 then it will be"no change" means previous state will be printed as present state
@@mahabirneogy7195 thanks brother 🙂
This truth table is different than taught in previous video. Is this for Active-low SR FF and previous one was for active high? I am having this doubt