Introduction to JK flip flop
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- Опубліковано 17 лют 2015
- Digital Electronics: Introduction to JK flip flop.
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Learned more in 20 minutes of these videos than a full month in my CMP ENG course. Life saver.
Now what are you doing in ur life?
@@last_time_I_pooped_was I'm a working electrical engineer and pursuing my PhD.
As an added note, I've never mentioned, used, or required knowledge about JK flip-flops since the computer engineering course at the time of the above comment. Everything is based on the D flip-flop.
@@last_time_I_pooped_was i was wondering this too
how in the world did you not learn about flip flop circuits
Pretty Dumb I guess
I dont understand .why it is getting dislikes..you are getting a great job sir..with a great teaching
because he calls latches flipflops
There are teacher of our college who didn't explain
@Prateek Patel okay. I'll watch .
Dislike are from those teachers who were expelled for not teaching well...
UA-cam removed dislike are you happy now ?
I had digital electronics paper today..al I did ystrdy was watching ur videos.and im nw here typing my gratitude. thank you so much brother...you have brought satisfaction in me.cos I really feel having learned something.
After doing a couple of hour of observation and trying different combination of gates for flip-flop I came up with these conclusions.
Things get really confusing when we moved to the J-K flip flop.
Let’s start from beginning,
We’ve two data storing elements i.e.
1: SR NOR Latch
2: SR NAND Latch
They work the same but their truth tables are completely opposite to each other. i.e.
SR NOR Latch truth table
S R Q
0 0 Memory state
1 0 1
0 1 0
1 1 Not used
SR NAND Latch truth table
S R Q
0 0 Not used
1 0 0
0 1 1
1 1 Memory state
After studying these basic memory elements. We moved to SR latches with “enable”. This enable is input to the two NAND gates along with Set and Reset (as in the circuit diagram shown in video). The output of these two NAND gates is input to the Latch (SR NAND). If we replace “enable” by “Clock” we would have a flip flop.
Let me ask you a question. Can’t we use any other combination of gates?
Of course, we can.
See the possible combinations which will work as an SR flip flop.
1. AND-NOR
2. NOR-NOR
3. OR-NAND
4. NAND-NAND (Used in video)
You must be thinking what about the other combinations?
5. NAND-NOR
6. OR-NOR
7. AND-NAND
8. NOR-NAND
These combinations (5 to 8) will not work as flip flop. Try making truth table for each of these combinations. After making truth table, You’ll realise that these circuits (5 to 8) are automatically going into “Invalid State” when the clock is Low/High depending upon the circuit configuration. Flip flop must follow one property, if clock goes Low or High, it must have a memory state. See these circuits
are not storing data we can’t use these combinations.
The only possible combinations which will work as an SR flip flop are:
1. AND-NOR
2. NOR-NOR
3. OR-NAND
4. NAND-NAND (Used in video)
Hope, it cleared your doubt till now.
But as we move to J-K and T flip flop. We again have some limitations.
We get J-K flip flop when we feedback Q’ to the top NAND gate and Q to the bottom NAND gate
Using this type of arrangement of feedback. Only two possible combinations will work i.e.
1. NOR-NOR
2. NAND-NAND
Did you see? We started with 8 combinations and end up having only two useful combinations for J-K and T flip flop.
If you want to use the remaining combinations for J-K and T flip flop
1. AND NOR
2. OR NAND
Then, these two combinations can also be used if we make some changes in the feedback arrangement.
Suppose, if we have an AND-NOR SR flip flop we want to make JK flip flop then we have to use this configuration,
“If Q is input to the top AND gate and Q’ is input to the bottom AND, using this configuration the remaining two (AND-NOR, OR-NAND) will also work.”
I tried every possible combination and their truth table. Everything in this video is correct and accurate.
Hope it helped you!
your stuff is kinda wrong in terms how it is tought in my school. Here truth tables are the same with any gates, what changes are the inputs and the scheme
IE in SR latch with nand if you give top input s and bottom input r while top output is q
then you will get the opposite of regular truth table however in my university that is considered a nonsensical trigger. You have to give both inputs reversed, so top input is 'not s' bottom is 'not r' ;;;; outputs: top 'q' bottom 'not q'
though there are other combination where the table would be correct as well IE
nR->nQ
nS->Q
and only difference of sr and jk is the 11 in sr is undefined and in jk is reversed.
Wow great..... excellent understanding
😨
thanx saved me a lot of time
Bhai logic gates ki sale lagi thi kya
u r simply amazing! i hope you get all the success u deserve
I have tried to understand JK flipflips for 15 years now and FINALLY I understand what they are, An SR latch with an extra feature ! TOGGLE. My goodness, THANK YOU !!
thank you so much for putting this much efforts and making it very clear and I'm really hoping that you are going to upload the the sequential circuits designing and analysis and the state digram because I have exam this week and can't find any good resources
Man, i just wanna thank you for your videos, they helped me out in Varsity...i graduated last year but, Thank you so much💪💪❤
for anyone having trouble remembering this, i suggest you think of it like this: Only when Q = 1, the device can be Reset, and only when Qn = 1, the device can be set. Just as a tip for remembering it more easily 😊
explained....the whole concept in a very simple manner,..... thank u sir.....
At 2:04 we have the truth table for Sr ff with nor gate but we are using the diagram of Sr with nand gate these two totally gives different outputs
yes same doubt..
that is sr filp flop with NAND gate and that is correct. you are talking about sr latch with nor gate.
Sir you are a legend. I hope you get very successful in your life!
Wow, your presentation was really helpful! Thanks :)
Man, you are awesome. I'm studying for my test and you are the only guy that I understand!
thank you so much for helping me.
I'll drop my PayPal contribution on your website tomorrow. keep the great work!
Sir, I am very thankful to you for this.aapke lectures se Maine bahut ache marks obtained kiye.warna meri reappear thi sir electronic mein.thanks sir......
I wish i found this channel sooner. finals are coming up.... gonna watch a few vids to save my grade loool
Thnku so much for making this things so easy for us☺ u were a life saver to me😊
"you have already
studied about the SR flip-flop and D flip-flop so what is the need to study the next type of flip-flop that is your third flip-flop"
YES EXACTLY WHAT I'M THINKING, WHYYYY
First time i understood toggling. You are legendary man🙏
Great Explanation, one in a million!
Thank you very much!
That was a wonderful presentation! However, I do wanna point out that there are two main variations on the SR Latch (which are used to synthesize the JK Flip Flop)...refer to the previous video as self-evidence. WHY DOES THAT MATTER? ==>> The NOR type preserves the memory state of Q, Q_bar whenever S = R = ‘0’; S = R = ‘1’ results in the forbidden state. The NAND gate simply inverts the relationship, where all ‘0’ is forbidden and all ‘1’ is the memory preservation state. I noticed that the SR schematic is NAND based, whereas its truth table is NOR based...an alleged contradiction, if you will. I’m not a seasoned pro at this, but I think my observation makes sense, and can be used to improve the insight that you provided. Again, great video, (& to the viewers, take the presentation with a grain of salt). :) I’ll keep watching, Neso Academy. Have a great day!
+Oswald Chisala this is really confusing me how can we use NAND based rs F-F while using NOR based f-f ??
PLEASE MAKE VIDEOS ON DIGITAL LOGIC FAMILIES (TTL, ECL, CMOS etc) and ADC and DAC conversions.
Your lectures are great.
Thank you so much for them.
he wouldve done them if you weren't screaming at him. thanks a lot.
Just discovered these lectures. Now I don't have to worry about my CC V
Thank u sir for providing such a nice explanations on the sequential circuits..it is really helpful to Me..
type sht
amazing job man! keep going !thanks for the help!
I think you are the reason for my success !!!!!
THANKS A LOT, ITS JUST GOT ME READY.
Thank you so much sir. You are simply marvelous.
Your lectures are very helpful.
Thanks sir, All your lectures are well explained. Thanks :)
Thanks again and again sir for your work
Thankuuuuuu sir
You really help us alot.
Clear concepts in a seconds.
You really make difficult subjects easy.
Here,T.T. for SR f/f using NOR gate and and the diagram for RS f/f using NAND gate, which is quite overwhelming if you are looking table and the diagram parallely , so nerds don't get confused 😕
thanks sir.
that's so better explained as compared to others
Hi NESO,
If Q is given back to J NAND gate
Q' is given back to K NAND gate,Also toggiling occurs. You proved that you are good teacher.And you has a knowledge sharing great habit.🙋🏻♂️
I understood the concept well thank you so much sir👍
Is it confusing only for me? :(
are you trying to tell me, with a JK flipflop and two high inputs, it will flipflop?
Madness!
PS, actually very helpful. Thankyou :)
Thank you very much for uploading these videos. Now I am able to understand digital electronics a bit.
But Sir, will you please do me a favour by uploading the positive and negative edge triggering of SR, D, JK and T flip flops because I am not able o understand these particular things in digital electronics.
Thank You.
Tq sir.this videos are very usefull to me.any one cam understand ur lecturing easily. Way of teaching i loved it thanq sir
this was grately helpful. I had a hard time understanding toggling
+ Neso Academy how did u know what is the value of Q and Q' , accept the last case where u assumed
U don't but if u see the nand truth table when ever one input is 0 then irrespective of 2 input we can say the output will always be 1.so if J=0 and K=1(0,1) input we take the Q=1 and then we pass this 1 as 2nd input of k and thus ~Q =0.
Hope this help
you guys are great. iam able to understand about flip flops. good job. all the best guys and thank you : )
In J-k flip flop you have made use of 3 input NAND gate with 1.J 2.clk and 3 .k
Until and unless we get all.3 input how will the gate work or there is previous some Q and Q bar going in 3 input NAND gate , please clarify it
i have learned so much things from you thank youu you are the best
It was really helpful
I apperciate your work!!!!
Sir can you make a series of videos on 8085 microprocessor please!!!...and thank you for your existing content too
Congratulations 👏👏🎊 sir for 1million subscribers , keep growing
Uyyyy7w
I m watching almost every 6 months
salute to neso academy very good explanation
Don't you think so, that clk. Must be edge triggered (as per diagram) ?
Excellent video!
your video is awesome.. thanks a lot
Happy teacher's day...Sir. Your videos helps me a lot. Please make video on electromagnetic.
Man, you are awesome.
sir in the sequential circuits playlist, you haven't added video of characteristic and excitation table of d flip flop.You directly moved onto JK flip flop. Please add it to the playlist too.
Sweet voice sir😁
Great explaination sir I was totally understanded thank you for sharing this sir♥️👌
I have a question. Initially you had shown a S- R Flip Flop with S and R as two inputs with clock pulse present. That indicates that the NAND gates present in the first level are two input NAND gates.
If this is the case then how a third input (Q or it's complement) can be added as one more input to these NAND gates? In this process the two input gates are changing to 3 input gates.
yes.. it can be done.. we have a separate IC for three input NAND gate (IC7410)
for me this tutorial is so good good job
Thank you so much, sir.
His way of teaching makes me feel like... It's an offline class. Mean face to face.
good clear explaination,thank you
You are amazing. Thank you!!!
sir ,i have been hearing your voice by this tutorial ,i just i want to see your face ,your tutorials are really awesome
see you are crossing in my way
did i do anything to u
i just like that video whats wrong with that . You said "gay" that was really annoyed me
so sry if i hurt You.plz dont cross my way.
He was actually replying to some other person's comments. But it seems like that other person has deleted his comments and this conversation looks one sided.
Can u recommend textbook on digital electronica
just awsome video tutorials....i have ever seen...@neso
that was rly helpful, thnx
Explaination method is excellent
Sir Can you please make videos on programming of 8051 microcontroller
It would help a lot of students.
Thank you.
awesome videos..helped a lot..thank you
you took j=0 k=1 as similar to sr flipflop
can you explain it on jk directly how it is coming that output ...without taking reference of sr flip flop..
Exactlyyyyy !
i need to understand that
simple to understand videos!
Isn't the truth table you have for the SRFF for the nor gate implementation?
It is so helpful sir.Thank u
Hi Neso Academy, your videos are really help full, thanks for the easy explanations.
for the JK flip flop i have a question, why are we considering the output of clk, S and R as Q(n+1) and why not just Q?
this is causing a lot of confusion since the value iof Q and Q(n+1) are opposites. please help !!
Both are same
yes
thanks to your video, i have understood now
so you explained the jk latch but how do we use jk latches to make JK flip flop?
Thank you sir🥺❤️
Thank you sir
Very good videos
hello there . i do have a very simple questions at 5:30 you said when we have 0 and 1 in SR latch the result actually is that Q =0 and not to 1 based on the table you have on your presentation any answer would be helpful .
marouane bicher you have to refer to basic SR Latch table . When Reset = 1, Qnot=0
@@munirahmoorman3602 thanks bro
Iam too wasted my time there
well that's just awesome thanks
If I assume Qn-1 = 1 and ~Qn-1 = 0, and I also set c=1, j=1 and k = 0, then the Inputs of the last nand gates (so the one for the latch) are both 0 and 1, which would result in Qn =1 and ~Qn = 1 if you go and check the network (not the truth table).
U are correct
Thank you sir for clarification toggle state
can i use it for blinking of two leds?
Great explaination and unorthodox English ❤😅
I still dont understand how the clock "locks" and "shift" the latches to next state :(
00:06 JK flip-flop provides an advantage over SR and D flip-flops.
00:51 Introduction to JK flip-flop
01:42 The JK flip-flop has two outputs Q and Q complement.
02:50 JK flip-flop and SR flip-flop have similar outputs except for the last case.
04:06 Analyzing the values for Q and Q complement
05:03 NAND SR latch can produce different outputs based on input changes
06:01 The JK flip-flop races between 0 and 1
06:58 JK flip flop output is the complement of the previous state.
EE101
thank you :3
Life Saver! Thanks a lot
Can you implement the jk flip-flop using SR NOR flip-flop
What do you mean by 3 inputs to a NAND gate?
Please give details
also upload video of semiconductor memory and asynchronous sequential logic
I just want to know how would the 3rd connection (which was not present in the sr FF) affect the 1st four output, I don't understand because you filled the same as SR FF..
1:00 Why does the logic diagram represents a SR flip-flop with NAND gate but the truth table is of a NOR gate SR flip-flop?
Amazing videos
isnt that a truth table for SR in a NOR?
I don't know why you have choosen as Q and Q complement different in last case... What does the meaning of last state if you taken as Different ? I don't know why... But I think there should be some different explanation to it....
Thank you
sir how can we assume ourr self the value of Q (4:20)
the value of Q will depend on the previous state before input becomes 1,1 . so the Q value doesnt matter, it could be 0 or 1 but the working will be same
sir while write output for inputs your not condidering q and q' inpus just writing outputs considerin only j and k and enable or clock