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Maharshi Sanand Yadav T
India
Приєднався 26 бер 2013
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What is Propagation Delay || #verilog || #ece || #vlsi || #vlsitraining
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Переглядів: 281
Відео
#1 || Number of Directories || bash scripting || #bashscripting
Переглядів 138Рік тому
#!/usr/bin/bash mkdir DIR1 DIR2 DIR3 DIR4 DIR5 ls -l | grep "^d" | wc -l UA-cam: ua-cam.com/users/maharshisanandyadav
parameters of .lib || cell rise, cell fall, rise transition, fall transition || .lib || #STA || #ece
Переглядів 416Рік тому
Thanks and Regards @maharshisanandyadav UA-cam: ua-cam.com/users/maharshisanandyadav
What is Rise Time (Tr), Fall Time (Tf) and Delay Time (Td)
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#risetime Rise time is like the morning sun for electronic signals-it's the time it takes for a signal to transition from a low to a high voltage level. #falltime Ah, the fall time, the counterpart to rise time! It's the duration it takes for a signal to move from a high to a low voltage level. It's like the sun setting on your waveform, bringing the day to a close. #delaytime In VLSI, delay ti...
Experiment: 8.a || CMOS NAND GATE || Schematic | Layout | DSCH 3.1 | Microwind
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A CMOS NAND gate is a type of digital logic gate that implements the logical operation of the NAND (NOT-AND) function using Complementary Metal-Oxide-Semiconductor (CMOS) technology. It takes multiple inputs and produces an output based on the logical NOT-AND operation. Here's how a 2-input CMOS NAND gate works: Inputs: The CMOS NAND gate has two input terminals labeled A and B. Transistor Conf...
1- bit Comparator || Gate Level Modelling || #vlsi #vlsidesign #tmsy
Переглядів 1 тис.Рік тому
A 1-bit comparator is a digital logic circuit that compares two binary numbers, each consisting of a single bit. It determines whether one bit is greater than, less than, or equal to the other bit. The output of the 1-bit comparator indicates the result of the comparison through specific output states, usually denoted as "greater than," "less than," or "equal to." Functionality: A 1-bit compara...
CMOS Inverter Schematic & Layout || Microwind 3.1 || #DICD_LAB || #ECE2020-2024 || 6th SEM || #ece
Переглядів 374Рік тому
#CMOSInverter #LogicGate #DigitalCircuits #ComplementaryMOS #MOSFET #IntegratedCircuits #SemiconductorDevices #ElectronicsDesign #VLSI #DigitalLogic A CMOS inverter, short for Complementary Metal-Oxide-Semiconductor inverter, is a fundamental logic gate used in digital integrated circuits. It consists of both n-channel and p-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) c...
Write structural Verilog HDL models for 4-bit binary adder and subtractor || #verilog
Переглядів 1,5 тис.Рік тому
#4BitAdder #4BitSubtractor #DigitalLogic #BinaryAddition #BinarySubtraction #DigitalCircuits #ComputerArchitecture #LogicGates #HardwareDesign #ArithmeticLogicUnit Link = www.tmsytutorials.com/4-bit-binary-adder-and-subtractor-verilog-code-for-4-bit-binary-adder-cum-subtractor/ A 4-bit adder cum subtractor is a digital circuit that can perform both addition and subtraction operations on 4-bit b...
Experiment 1.b || 4-bit adder and subtractor || Verilog Code, Working Explanation || #verilog
Переглядів 7 тис.Рік тому
#4BitAdder #4BitSubtractor #DigitalLogic #BinaryAddition #BinarySubtraction #DigitalCircuits #ComputerArchitecture #LogicGates #HardwareDesign #ArithmeticLogicUnit link = www.tmsytutorials.com/4-bit-binary-adder-and-subtractor-verilog-code-for-4-bit-binary-adder-cum-subtractor/ A 4-bit adder cum subtractor is a digital circuit that can perform both addition and subtraction operations on 4-bit b...
3T DRAM || PC414EC || 3 Transistor Dynamic Random Access Memory || #vlsidesign
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#3TDRAM #DynamicRAM #MemoryTechnology #TransistorMemory #EnhancedPerformance #DataReliability #MemoryCells #MemoryArchitecture #ReadOperations #WriteOperations #DataIntegrity #PowerConsumption #CellSize #MemorySystems #TechEnthusiasts #TechnologyExplained #MemoryStorage #DataRetrieval #electronics Welcome to our UA-cam channel! In this video, we will be exploring the fascinating world of 3 Tran...
1T DRAM || PC414ECE || 1 Transistor Dynamic Random Access Memory
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#1TDRAM #DynamicRAM #MemoryTechnology #TransistorMemory #EfficientMemory #CompactMemory #MemoryCells #MemoryArchitecture #ReadOperations #WriteOperations #PerformanceCharacteristics #ScalingDown #ProcessNodes #HighDensityMemory #ElectronicDevices #TechEnthusiasts #TechnologyExplained #MemoryStorage #DataRetrieval #electronicstutorial Welcome to our UA-cam channel! In today's video, we will be d...
2-bit up counter design and implementation using SR-FF || synchronous || positive-edge trigger
Переглядів 1,2 тис.Рік тому
#2BitUpCounter #SRFlipFlop #SynchronousCounter #PositiveEdgeTriggered #DigitalDesign #SequentialCircuits #StateTable #StateDiagram #CombinationalLogic #BinaryCounter #SynchronousDesignMethodology #SequentialLogic #ClockSignal #DigitalElectronics #LogicDesign #FPGAImplementations #ElectronicsTutorial #DigitalCircuitApplications #FrequencyDividers #AddressGeneration #ControlSystems #DigitalLogic ...
verilog code of SR-FF || positive edge trigger || #tmsy
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#SRFlipFlop #SetResetFlipFlop #SequentialLogic #DigitalCircuits #TruthTable #TimingDiagrams #PositiveEdgeTriggered #DigitalElectronics #ComputerScience #LogicGates #FlipFlops #LogicDesign #ElectronicsTutorial #DigitalSystems #LogicGatesTutorial #LogicDesignBasics #FlipFlopTutorial #LogicCircuitDesign #DigitalLogicExplanation Title: Understanding the SR Flip-Flop - Sequential Logic Explained Des...
4x4 NOR Based ROM Array || #NORBasedROMArray#4x4ROMArray#Readonlymemory#ROMCircuit #tmsy
Переглядів 6 тис.Рік тому
Unit-3 Sub-System Design #NORBasedROMArray #4x4ROMArray #Readonlymemory #ROMCircuit #DigitalLogicDesign #MemoryCells #IntegratedCircuits #ComputerEngineering #ElectronicsEngineering #CircuitDesign Facebook: tmsy.tutorials Instagram: tmsy_tutorials Website: www.tmsytutorials.com/
Path Sensitization Method || #unit5 #pc702ec #vlsi #ece #osmaniauniversity #vlsidesign #engineering
Переглядів 15 тис.Рік тому
Path Sensitization Method || #unit5 #pc702ec #vlsi #ece #osmaniauniversity #vlsidesign #engineering
Source Degenerated Current Mirror || #vlsi #ece #vlsidesign #pc702ec #tmsy
Переглядів 1,5 тис.Рік тому
Source Degenerated Current Mirror || #vlsi #ece #vlsidesign #pc702ec #tmsy
NMOS Current Mirror || Output Impedance, Resistance || #tmsy #vlsi #vlsidesign #engineering #ece
Переглядів 879Рік тому
NMOS Current Mirror || Output Impedance, Resistance || #tmsy #vlsi #vlsidesign #engineering #ece
Small Signal Equivalent Model for NMOS, I.e. MOSFET #ece #vlsi #vlsidesign #tmsy
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Small Signal Equivalent Model for NMOS, I.e. MOSFET #ece #vlsi #vlsidesign #tmsy
What is Current Mirror || Why is Current Mirror || NMOS Current Mirror || #tmsy #vlsidesign #vlsi
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What is Current Mirror || Why is Current Mirror || NMOS Current Mirror || #tmsy #vlsidesign #vlsi
Logic Gates Implementation using Multiplexer #ece #vlsi #osmaniauniversity #engineering #vlsidesign
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Logic Gates Implementation using Multiplexer #ece #vlsi #osmaniauniversity #engineering #vlsidesign
Stick Diagram of CMOS NOT GATE || CMOS Inverter || #inverter #cmos #gate #tmsy #vlsi #vlsidesign
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Stick Diagram of CMOS NOT GATE || CMOS Inverter || #inverter #cmos #gate #tmsy #vlsi #vlsidesign
How to Take Attendance in MCET ERP || #MCET || #TMSY #microsoft
Переглядів 942 роки тому
How to Take Attendance in MCET ERP || #MCET || #TMSY #microsoft
NMOS Inverter Delay #VLSI #inverter || The Delay unit in MOS Circuits #ece #osmaniauniversity #tmsy
Переглядів 1,2 тис.2 роки тому
NMOS Inverter Delay #VLSI #inverter || The Delay unit in MOS Circuits #ece #osmaniauniversity #tmsy
Designing a Full Adder using CMOS Schematic| #DesigningFullAdder #CMOSSchematic #DigitalLogic #VLSI
Переглядів 5102 роки тому
Designing a Full Adder using CMOS Schematic| #DesigningFullAdder #CMOSSchematic #DigitalLogic #VLSI
Output Conductance gds || #conductance || #ece #vlsi #osmaniauniversity
Переглядів 1,2 тис.2 роки тому
Output Conductance gds || #conductance || #ece #vlsi #osmaniauniversity
Transconductance gm || #conductance || #ece #vlsi #osmaniauniversity #engineering
Переглядів 9962 роки тому
Transconductance gm || #conductance || #ece #vlsi #osmaniauniversity #engineering
Schematic for CMOS HALF ADDER || #schematics || #vlsi || #vlsidesign || #ece || #osmaniauniversity
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Schematic for CMOS HALF ADDER || #schematics || #vlsi || #vlsidesign || #ece || #osmaniauniversity
CMOS OR SCHEMATIC || #schematics #madeeasyfaculty #ace #ece #vlsidesign #vlsi
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CMOS OR SCHEMATIC || #schematics #madeeasyfaculty #ace #ece #vlsidesign #vlsi
Final Schematic of CMOS XNOR || #schematics #madeeasyfaculty #ace #ece #vlsidesign #vlsi
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Final Schematic of CMOS XNOR || #schematics #madeeasyfaculty #ace #ece #vlsidesign #vlsi
CMOS XNOR Boolean Expression to draw Schematic | #schematics #madeeasy #ace #ece #vlsidesign #vlsi
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CMOS XNOR Boolean Expression to draw Schematic | #schematics #madeeasy #ace #ece #vlsidesign #vlsi
Sir 0.75 ko 2 se multiply karenge to 1.50 aayega n....?
Thanks a lot finally I understand the concept
Can we get this notes of yours sir
sir you said that we need to consider h=1 due to SA-1 fault but at the end when are getting different combinations or possibilities for a and b why do consider all cases is it because both and b are primary inputs?
Bad explanation bad representation
Sir how we install microwind and dsch
Is we need to write source code of 2_4 decoder in program ?
Yes first we need to write code for 2x4 decoder then next step is to instantiate it
How about 4 bit counter?
Sir, isn't it that same ( Q is both output and clk ) is up counter?
Jhant logic explain Kiya h bkl
In answer (1.0000011×2⁵ ) why we have taken 2 to the power of 5?
I think the power here will signify the digits you need to skip before the last digit
In binary representation, we take 2
sir why we ignore decimal part 1 in 1.0000011 when we write floating point representation ?
Because it represents the sign
thank you sir .I understood clearly
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Nailed it bro ❤ What an explanation
Thank you so much Anna, video chaala useindhi 🙏🫂
Thanks for letting me know Check the code from this site www.tmsytutorials.com/write-a-verilog-hdl-program-in-hierarchical-structural-model-for-16x1-mux-realization-using-4x1-mux/
Anna , RTL for bidirectional buffer, code and text bentch explain chai Anna please
What if they don't mention use kmap for simplification purpose?? Then how will we get equation for the nor gate??
Using Boolean expression ??
There are some methods to simplify the boolean expression : 1)k map 2)Quin-Mc cluskey 3)Algebric So if they didnt mention about the k map they must mention either of 2 or 3
Why de morgan rule not applied....?
BEST EXPLANATION AWESOME 😊
any one can explain how in E-127. where the 127 comes from??
This just saved me.✌🏽
Thank you for this tutorial.
Very easy to get it from ur videos 🎉
www.tmsytutorials.com/3x8-decoder-realization-using-a-2x4-decoder/