If you derive your clock signals from the same clock source via a divider, than those clock signal are always in sync relative to each other and therefore should solve your CDC problem
LoL, I've always seen people do idyuitic things. Like connecting mcus using uart, while they could be using some better, higher bandwidth/bitrate and faster communication like i2c or serial or even rs232, rs422 or even rs485 along with a shared RTC. But nooo! They'll usually use the inefficient, uart for inter device communication, with bad synchronisation. We'll tbh I'm no expert, but it just makes me cringe slightly.
@@yasirrakhurrafat1142 Higher bitrate means also higher EMI and therefore complex PCB design which lead to higher PCB cost (If you want your communication/embedded device to work reliable). I don't see any problems in using UART over i2c. If you don't need the speed and don't need a bus system to communicate to other devices, UART is fine. You can use i2c, but then you have to make sure to do impedance matching, place a pull-up resistor (i2c is open drain/collector) and so on. I work for a big IC company (MCU) and we have an example board with 2 MCUs that communicate over UART. Also, you say that serial is better than UART but UART is a serial communication. RS232 is also using UART to transfer data. RS232, RS422, RS485 describes how the digital signal should electricaly behave to send over 0s and 1s.
@@TheKluxi1so SPI is end2end without external pull ups? How difficult is it to arrange chips in a way that SPI traces don’t cross and are not too long? So your EMI solved even on a 2 layer PCB. And 4 layer is cheap for amateurs.
How do you deal with all the chemicals? I guess I would like to understand how chemical processes allow us to deposit a high quality film without holes. Kinda like soap. Does photoresist contain soap? What about ion beams? I only used argon. I guess that we cannot use aggressive chemicals here? I would love to see a 3d printer for hot, pure copper wire. Some mini-hammers to thin it down just before laying down. Scale it from PCB scale (no etching) to packages to on-die. Layup glas fibers with hollow cores for isolation. Gas tight seal ceramic package. Vacuum.
@ FPGA is not real to me. It has a use in a board with many chips and GPIOs and short latencies, but for that we need to go far beyond amateur stuff. Even Emulators of game consoles are not provable worse on ARM. Controller input is just slow, and Video / Audio can have a whole line of latency. Just don’t run a fat OS or CPU. 1.8 GHz AARCH64 give you a million instructions per scanline.
Great job! I would like to see you try to go in more details as it seems very interesting. You literally have pushed months of work in 10 minutes :) Really like the abstract explanation, they are easy to understand and useful to hear. Keep up the good work!
nice, i have also made my cpu, but more the planning and some building, im hoping i can one day get it on a silicon wafer like that onoe guy on yt, would be very cool
Thanks ! If you want to build a cache and AXI stuff (which I found to be the hardest), you'll find clues in the fpga_edition folder in the repo ;) glhf
Thanks ! I almost did one too but figured redstone circuits were a bit too niche for me to get a job later haha. Definitely something I may try in the future. If I do, I'll hit you up by answering this comment for sure ! Have a good day.
Any chance it will be like 4004 or 8008 using DRAM for registers and stack (and for advancing the refresh counter itself?) ? Or do you build a Blinkenlicht LED matrix as register file? Notice how the CPU shown in this video has many registers. A 6502 probably gets away with registers as a second thought. DRAM over GPIO would really show off the FPGA because you need fast signal handling.
10:00 Time domains. I actually don't understand why engineers were so eager to cross time domains in the past. In Atari Jaguar for example the chipset allows you to put two independent crystals on the PCB to do what? I mean, I could understand if we want to be able to switch ( while power is off?) between PAL and NTSC color carrier frequency. Is there really no way to generate both by integer subdivision of 60 MHz ? But there is no reason for the digital logic to have its own clock. Digital logic ( genlock on Amiga ) is happy to run any clock below its (temperature) limit, or at least an octave width of acceptable frequencies even in "dynamic" implementations. Time domains are needed when light pulses are created by the pits in a CD, or electrical pulses by magnetic domains in the HDD surface. Or when you link two Gameboys together. Or is there a Master, a dedicated server, a hub as in twisted pair ethernet ( certainly not in coax ethernet)?
The whole goal of this project is to learn. I wanted to use different clocks domains to "simulate" a slower memory, which is usually what happens in "real world" systems. But in the end, I figure it wasn't worth the hustle. Sometimes, we just like to over-engineer stuff ;)
@ still please tackle that problem later on. After all, for PCIExpress you have to “synthesise” the clock at the receiver. Is this about frequency or only a const phase? It would be cool to show the internal workings of DRAM, by constructing a memory controller for “bare bone” async fast page mode RAM from the AtariJaguar or PC up to 1996. Maybe the FPGA has fast ADCs to check the signal in situ?
Hey im also working on a riscv related project (pipelined cpu in our case) where we have already made the cpu core and we are currently doing sensor testing to integrate a couple of sensors with the cpu along with a bluetooth module to run a bot did you try handshaking or double flip flop instead of just avoiding CDC all together? Im asking just because we are almost done with the sensor integration and next stage we will be actually integrating all of them together to make a functional bot and if you have tried any of this please do share the results because the cpu will be running on the in house 50mhz whereas rest all will be running on scaled down 3 or 1 mhz frequencies
Hey, by the look of your project description, chances are you have more to tech me than I have to teach you haha. But regarding CDC, yes you can make sure the data is okay by using multiple FFs (Flip Flops) or some FIFOs to pass data alongside some handshake signals to add context to the data coming from the other clock domain. But I did not really need it so I figured I'll only us oen clock ;)
Like another commenter said: integer scaling of frequencies is no problem. The problem arises when you use two crystals like commodore did in their C128 or their 5114 disk drive. CPUs always ran at multiples of the external clock: 68k runs at 8 MHz, but memory only sees 4 MHz. 386 runs at 16, mainboard only sees 8. 486 DX2 , 486 DX4 Woz of Apple was clever and let the drive controller run with the CPU clock. The Atari Jaguar has a clock divider integrated on one chip, but the designers were smart to avoid clock skew. All chips (including Jerry) get the bus relevant clock from same length traces on the PCB. Now just tell me why the bus trace itself is so long, winding over the whole PCB back and forth.
I dont fully understand what your cpu can do now, like what did you do so you know it works? I guess you didnt install linux on it or something like that :D Did you just let it calculate something and check the output? How did you test it? Im having a test on similar stuff soon, I apprecieate this video, it made me actually want to open the script and read into it
Thank you ! Basically my CPU is an MCU (micro controller), meaning it can run basic programs but can't do the more complex memory manipulation stuff necessary to run a whole OS. In the video I blinked LEDs but now that this works reliably, I can do pretty much anything, as long as it's suitable for an MCU. See it as an Arduino, except it's DIY. For the testing I did absolutely nothing on FPGA if not see for myself is the LEDs blinked haha. But I made pretty extensive testing in the testbenches for the HDL.
Would you think a nice way to show off the speed of the FPGA would be to control a quadcopter? Each GPIO controls one power Mosfet. Back emp as input. Or a model single cyclinder combustion engine with crankshaft rotational encoder, spark plug, injector timing. Or active suspension. Or controlling the exact position of an electron beam in a CRT . Or controlling a CD drive (focus, track) ? Or a memory controller for magnetic core memory. I figured out that you need to capture the response pulse in a timely fashion. As with DRAM: if we have no other memory to keep a row, wouldn’t we need two memories and ping pong the data rows with a part of it going through the ALU? An Journalling? Where is the bootstrap?
I have an Zynq UltraScale+ RFSoC 4x2 board ( yes I know, she's HOT ) and I was planning to make a pipelined core on it ( I had made one for MIPS last year by using python ) and now I am trying to make one RISCV, I am absolutely new to FPGA though, just learning AXI itself seems really hard, any suggestions ( other than AMD Xilinix's official documentation :cry :sad ) Also LOVE YOUR CONTENT, you could be the fireship but for electronics, soc, cpu/gpu nerds
Damn bro where did you get that board ? If you need the real basics I have some material on my channel and on my blog : 0bab1.github.io/BRH/. Once you grasp the whole concept of doing basic stuff with FPGAs (don't need to master AXI, most of the time it's just plug and play), then you can start tackling the HOLY CORE tutorial to have guidelines in the first stages of your project and some inspiration if you struggle on the same parts as I did. Thank you ! And good luck with your project ! NOTA: by fpga basic I would say it's good to know the following : -> Blink an LED -> Blink an LED using a custom AXI IP -> Use DMA to move data around (fast) -> Design testbenches
Terry Davis walked so you can run. And run you'll need because the FBI are gonna get to you sooner or later, just how they got to Terry. Great content, keep em coming :)
Hey, I used an FPGA to use my CPU in the real world (which is not like using a "real" ASIC) I think you are refering to programs like TinyTapeout which allows (almost) anyone to make a tapeout of a chip. In this case you might want to make a multi-cycle core (which relies on a FSM, much slower) as they take less space on the final tapeout. Unfortunately I did not cover multicycle cores in the HOLY CORE Course, nor VLSI notions (yet)
@@BRH_SoC 6502 was famous for using often only two cycles per instruction and was smaller than Z80. ARM2 is single cycle (doing ALU and barrel shift within this cycle) and only half the transistor count than the 68k. So you want to save the pipeline registers? Ah, and all those pipeline hazard stuff. Shameless plug: AtariJaguar JRISC did not want to pay to solve all those hazards and used the shorter pipeline of ARM instead of the faster pipeline of MIPS. Canonical MIPS and hence canonical RISCV just never need a wait state on a 3 port register file, while on ARM and JRISC congestion can happen. So why not more ports? I guess that with 32 registers that would be very expensive. JRISC already only uses one port on the file. This saves a lot of transistors. A lot of computers ( PDP-11s , dataport 2000 ) used a serial ALU because all this configurations for different instructions need a lot of transistors.
Do you know how the SH2 cores in the Sega 32x work together? Or the JRISC cores in AtariJaguar? I read that Hitachi added some special command? Cores have their own cache, and so developers have to insert cache flush instructions into their code as on N64 to let the CPU talks with the RSP. I read that the i860 got bus snooping in a second revision. I think it means that two core can load the same data, and when one of them flushes its cache, the other one recognizes the addresses and updated its own cache?
Building chip from scratch. Then building you oun kernel Then bhilding os Then building software that run os this processor That should be enough for one man entilre life 😂
Team work and community are key aspects in modern society and enterprises. Communicate with others . Try out their Kernal on your CPU. Use Linux as OS. Or what the 8-bit guy did.
Hi, can you elaborate ? As @ArneChristianRosenfeldt already replied, most of the logic is comb logic and the clock is mostly here to increment the program counter and apply writes to memory. Is it about some more obscure computer science theory notations that I'm missing ?
@ yeah, just, this is specifically about this media channel and the presentation. Also I wanted to discuss this with other authors because the use of these effects is widespread and not specific to you. Sorry that my short version came over so negative.
If you derive your clock signals from the same clock source via a divider, than those clock signal are always in sync relative to each other and therefore should solve your CDC problem
LoL, I've always seen people do idyuitic things.
Like connecting mcus using uart, while they could be using some better, higher bandwidth/bitrate and faster communication like i2c or serial or even rs232, rs422 or even rs485 along with a shared RTC. But nooo!
They'll usually use the inefficient, uart for inter device communication, with bad synchronisation.
We'll tbh I'm no expert, but it just makes me cringe slightly.
@@yasirrakhurrafat1142 Higher bitrate means also higher EMI and therefore complex PCB design which lead to higher PCB cost (If you want your communication/embedded device to work reliable). I don't see any problems in using UART over i2c. If you don't need the speed and don't need a bus system to communicate to other devices, UART is fine. You can use i2c, but then you have to make sure to do impedance matching, place a pull-up resistor (i2c is open drain/collector) and so on.
I work for a big IC company (MCU) and we have an example board with 2 MCUs that communicate over UART.
Also, you say that serial is better than UART but UART is a serial communication. RS232 is also using UART to transfer data. RS232, RS422, RS485 describes how the digital signal should electricaly behave to send over 0s and 1s.
@@TheKluxi1so SPI is end2end without external pull ups? How difficult is it to arrange chips in a way that SPI traces don’t cross and are not too long? So your EMI solved even on a 2 layer PCB. And 4 layer is cheap for amateurs.
Why aren’t u fabbing your own silicon in ur garage cmon catch up
I mean, I saw a dude doing this once on UA-cam. So yeah I gotta catch up
How do you deal with all the chemicals? I guess I would like to understand how chemical processes allow us to deposit a high quality film without holes. Kinda like soap. Does photoresist contain soap? What about ion beams? I only used argon. I guess that we cannot use aggressive chemicals here? I would love to see a 3d printer for hot, pure copper wire. Some mini-hammers to thin it down just before laying down. Scale it from PCB scale (no etching) to packages to on-die. Layup glas fibers with hollow cores for isolation. Gas tight seal ceramic package. Vacuum.
@@ArneChristianRosenfeldt search FPGA
@ FPGA is not real to me. It has a use in a board with many chips and GPIOs and short latencies, but for that we need to go far beyond amateur stuff. Even Emulators of game consoles are not provable worse on ARM. Controller input is just slow, and Video / Audio can have a whole line of latency. Just don’t run a fat OS or CPU. 1.8 GHz AARCH64 give you a million instructions per scanline.
@@BRH_SoC He was Sam Zeloof, right?
Pure passion.
Great job! I would like to see you try to go in more details as it seems very interesting. You literally have pushed months of work in 10 minutes :) Really like the abstract explanation, they are easy to understand and useful to hear. Keep up the good work!
Thank you ! This is heartwarming :) I stiil have to fond a find a balance between explanations and vulgarizing indeed, it's very tricky haha
Underrated channel!
nice, i have also made my cpu, but more the planning and some building, im hoping i can one day get it on a silicon wafer like that onoe guy on yt, would be very cool
I have this specific project on my todo list too ;) how do you plan on getting the chip manufactured ? I planned on using tinytapeout on my side.
awesome! currently working on an RV32I core myself
Thanks ! If you want to build a cache and AXI stuff (which I found to be the hardest), you'll find clues in the fpga_edition folder in the repo ;) glhf
@BRH_SoC thanks! I played with AXI4 a while ago and it is indeed a nerdy little protocol lmao. Will refer to your repo 🫡
@@BRH_SoC thanks! AXI is indeed a very nerdy protocol lmao
Nice! I made a reference implementation of RV32I in Minecraft some time ago...
Thanks ! I almost did one too but figured redstone circuits were a bit too niche for me to get a job later haha. Definitely something I may try in the future. If I do, I'll hit you up by answering this comment for sure ! Have a good day.
Cool rafale on tthe wall)
A man of culture I see
Watching this as I'm developing an 8-bit cpu 🥲😂
Any chance it will be like 4004 or 8008 using DRAM for registers and stack (and for advancing the refresh counter itself?) ? Or do you build a Blinkenlicht LED matrix as register file? Notice how the CPU shown in this video has many registers. A 6502 probably gets away with registers as a second thought.
DRAM over GPIO would really show off the FPGA because you need fast signal handling.
Glhf bro ;)
compooter 🤓
Yes😂😂😂😂
10:00 Time domains. I actually don't understand why engineers were so eager to cross time domains in the past. In Atari Jaguar for example the chipset allows you to put two independent crystals on the PCB to do what? I mean, I could understand if we want to be able to switch ( while power is off?) between PAL and NTSC color carrier frequency. Is there really no way to generate both by integer subdivision of 60 MHz ? But there is no reason for the digital logic to have its own clock. Digital logic ( genlock on Amiga ) is happy to run any clock below its (temperature) limit, or at least an octave width of acceptable frequencies even in "dynamic" implementations. Time domains are needed when light pulses are created by the pits in a CD, or electrical pulses by magnetic domains in the HDD surface. Or when you link two Gameboys together. Or is there a Master, a dedicated server, a hub as in twisted pair ethernet ( certainly not in coax ethernet)?
The whole goal of this project is to learn.
I wanted to use different clocks domains to "simulate" a slower memory, which is usually what happens in "real world" systems. But in the end, I figure it wasn't worth the hustle.
Sometimes, we just like to over-engineer stuff ;)
@ still please tackle that problem later on. After all, for PCIExpress you have to “synthesise” the clock at the receiver. Is this about frequency or only a const phase?
It would be cool to show the internal workings of DRAM, by constructing a memory controller for “bare bone” async fast page mode RAM from the AtariJaguar or PC up to 1996. Maybe the FPGA has fast ADCs to check the signal in situ?
please keep making more content
I'll try ;)
HOLY CORE
Hey im also working on a riscv related project (pipelined cpu in our case) where we have already made the cpu core and we are currently doing sensor testing to integrate a couple of sensors with the cpu along with a bluetooth module to run a bot did you try handshaking or double flip flop instead of just avoiding CDC all together? Im asking just because we are almost done with the sensor integration and next stage we will be actually integrating all of them together to make a functional bot and if you have tried any of this please do share the results because the cpu will be running on the in house 50mhz whereas rest all will be running on scaled down 3 or 1 mhz frequencies
Hey, by the look of your project description, chances are you have more to tech me than I have to teach you haha. But regarding CDC, yes you can make sure the data is okay by using multiple FFs (Flip Flops) or some FIFOs to pass data alongside some handshake signals to add context to the data coming from the other clock domain. But I did not really need it so I figured I'll only us oen clock ;)
Like another commenter said: integer scaling of frequencies is no problem. The problem arises when you use two crystals like commodore did in their C128 or their 5114 disk drive.
CPUs always ran at multiples of the external clock: 68k runs at 8 MHz, but memory only sees 4 MHz. 386 runs at 16, mainboard only sees 8. 486 DX2 , 486 DX4
Woz of Apple was clever and let the drive controller run with the CPU clock. The Atari Jaguar has a clock divider integrated on one chip, but the designers were smart to avoid clock skew. All chips (including Jerry) get the bus relevant clock from same length traces on the PCB. Now just tell me why the bus trace itself is so long, winding over the whole PCB back and forth.
In before this video blows up! Awesome work
Thank you !
I know you are French before you started talking - via drawing of Dassault Rafale behind you!
Another men of culture ! Glad to have you here
I dont fully understand what your cpu can do now, like what did you do so you know it works? I guess you didnt install linux on it or something like that :D Did you just let it calculate something and check the output? How did you test it? Im having a test on similar stuff soon, I apprecieate this video, it made me actually want to open the script and read into it
Thank you !
Basically my CPU is an MCU (micro controller), meaning it can run basic programs but can't do the more complex memory manipulation stuff necessary to run a whole OS.
In the video I blinked LEDs but now that this works reliably, I can do pretty much anything, as long as it's suitable for an MCU. See it as an Arduino, except it's DIY.
For the testing I did absolutely nothing on FPGA if not see for myself is the LEDs blinked haha.
But I made pretty extensive testing in the testbenches for the HDL.
Would you think a nice way to show off the speed of the FPGA would be to control a quadcopter? Each GPIO controls one power Mosfet. Back emp as input. Or a model single cyclinder combustion engine with crankshaft rotational encoder, spark plug, injector timing. Or active suspension. Or controlling the exact position of an electron beam in a CRT . Or controlling a CD drive (focus, track) ?
Or a memory controller for magnetic core memory. I figured out that you need to capture the response pulse in a timely fashion. As with DRAM: if we have no other memory to keep a row, wouldn’t we need two memories and ping pong the data rows with a part of it going through the ALU? An Journalling? Where is the bootstrap?
I have an Zynq UltraScale+ RFSoC 4x2 board ( yes I know, she's HOT ) and I was planning to make a pipelined core on it ( I had made one for MIPS last year by using python ) and now I am trying to make one RISCV, I am absolutely new to FPGA though, just learning AXI itself seems really hard, any suggestions ( other than AMD Xilinix's official documentation :cry :sad )
Also LOVE YOUR CONTENT, you could be the fireship but for electronics, soc, cpu/gpu nerds
Damn bro where did you get that board ?
If you need the real basics I have some material on my channel and on my blog : 0bab1.github.io/BRH/.
Once you grasp the whole concept of doing basic stuff with FPGAs (don't need to master AXI, most of the time it's just plug and play), then you can start tackling the HOLY CORE tutorial to have guidelines in the first stages of your project and some inspiration if you struggle on the same parts as I did.
Thank you ! And good luck with your project !
NOTA: by fpga basic I would say it's good to know the following :
-> Blink an LED
-> Blink an LED using a custom AXI IP
-> Use DMA to move data around (fast)
-> Design testbenches
Terry Davis walked so you can run. And run you'll need because the FBI are gonna get to you sooner or later, just how they got to Terry.
Great content, keep em coming :)
I'll recognise them, they glow in the dark ;)
Thank you
Hey what cpu nm did you build? Im asking couse in algeria we will build our first 65nm cpu in March 2025.... But I think this is a little late
Hey, I used an FPGA to use my CPU in the real world (which is not like using a "real" ASIC)
I think you are refering to programs like TinyTapeout which allows (almost) anyone to make a tapeout of a chip.
In this case you might want to make a multi-cycle core (which relies on a FSM, much slower) as they take less space on the final tapeout.
Unfortunately I did not cover multicycle cores in the HOLY CORE Course, nor VLSI notions (yet)
@@BRH_SoC 6502 was famous for using often only two cycles per instruction and was smaller than Z80. ARM2 is single cycle (doing ALU and barrel shift within this cycle) and only half the transistor count than the 68k. So you want to save the pipeline registers? Ah, and all those pipeline hazard stuff. Shameless plug: AtariJaguar JRISC did not want to pay to solve all those hazards and used the shorter pipeline of ARM instead of the faster pipeline of MIPS. Canonical MIPS and hence canonical RISCV just never need a wait state on a 3 port register file, while on ARM and JRISC congestion can happen. So why not more ports? I guess that with 32 registers that would be very expensive. JRISC already only uses one port on the file. This saves a lot of transistors. A lot of computers ( PDP-11s , dataport 2000 ) used a serial ALU because all this configurations for different instructions need a lot of transistors.
Any more informations about Algeria cpu?
👏👏👏
POGGERS
Great, you made a single core CPU, next challenge is to make that core better and add another one, while making them work together...
Do you know how the SH2 cores in the Sega 32x work together? Or the JRISC cores in AtariJaguar? I read that Hitachi added some special command? Cores have their own cache, and so developers have to insert cache flush instructions into their code as on N64 to let the CPU talks with the RSP. I read that the i860 got bus snooping in a second revision. I think it means that two core can load the same data, and when one of them flushes its cache, the other one recognizes the addresses and updated its own cache?
Multi core computing looks like some real messy stuff haha, meaning I HAVE to do it indeed
4:54 There's no way bro started playing jewish music 😭
I'm not paying for a damn instruction set architecture !
Building chip from scratch.
Then building you oun kernel
Then bhilding os
Then building software that run os this processor
That should be enough for one man entilre life 😂
Team work and community are key aspects in modern society and enterprises. Communicate with others . Try out their Kernal on your CPU. Use Linux as OS. Or what the 8-bit guy did.
The average Terry Davis experience ;)
have you considered combinatory logic? it would be very interesting... let me know if interested
Uh for what? At some point you have to : program counter . He already said that he debugged a huge logic block (combinatorial).
Hi, can you elaborate ? As @ArneChristianRosenfeldt already replied, most of the logic is comb logic and the clock is mostly here to increment the program counter and apply writes to memory.
Is it about some more obscure computer science theory notations that I'm missing ?
02:31 I dunno who cares about the environment, but all the flicker is not helping to keep the video small end low carbon emission.
You can read the video description for this kind of inquiry.
Best regards.
@ yeah, just, this is specifically about this media channel and the presentation. Also I wanted to discuss this with other authors because the use of these effects is widespread and not specific to you. Sorry that my short version came over so negative.
No worries, maybe I read it wrong ;)