LDO basics: Dropout voltage
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- Опубліковано 4 сер 2024
- Visit the TI LDO homepage to learn more about the TI LDO Portfolio.
www.ti.com/ldo
This video will go over what an LDO is and discuss the importance of dropout
voltage in an LDO, as well as other variables for LDO accuracy. An
application will demonstrate the importance of dropout voltage when designing
as dropout voltage can affect the desired output of an LDO. The designer must
keep the input voltage and dropout voltage in mind when using an LDO.
Furthermore, PMOS and NMOS architectures used in LDO's will be covered as
this has the most impact to the dropout voltage.
Need Help? Visit the support and training tab from the LDO homepage.
www.ti.com/power-management/l...
Read the corresponding blog post, LDO Basics: dropout.
e2e.ti.com/blogs_/b/powerhous... - Наука та технологія
Explanation is great! i don't know why everyone complaining about this!
Make simplified explanation, this one is even more complicated than the one in my books, use practicals that's y we come to UA-cam to visually see not to listen to someone reading for us what we left in the books
Exactly. I had expected a simple explanation and introduction in first video
You're teaching very fast. Not easy to be understood by beginners
You made it more complicated than necessary.
LOL
Why did you change pin convention on what was standard for 40+ years? Why is pin 1 no longer input but GND? Why is the tab on a standard positive volt regulator now Vout?
how to do jumper ldo ic
So it is better to have a very low dropout voltage
Not bad, the video explains basics of LDO and points attention to the dependence of dropout voltage on various variables. Volume should be higher though. Thank you !
isn't there a volume button on your device
@@kwekker There is, but even when cranked up it was low.
Hi Sir,
what does the output current means?
I think that this value depends on the load condition as the output voltage is fixed!
it is the max current that it can supplied.
This LDO diagram at 3:15 is showing positive feedback, did you mean negative feedback?
It's positive sign, but negative feedback, as the PMOS has inverted signal behavior, in relation to the NMOS. So the higher the op-amp voltage, the lower will be Vout, and this 2 will be balanced to reach the setpoint.
to add on, the PMOS here acts as a CS (commons source) amplifier, which gain is negative. Hence, the output (at drain) is feedback to the positive terminal for negative feedback
The volume is too low.
I was searching why is a dropout even there
👍
TKQ
ua-cam.com/video/iw4z07oJGq0/v-deo.html
Here you are saying that 175mV is the MAX DO voltage and WHY you are assuming that the LDO will ALWAYS drop the Input voltage by that value?
If there any one need ldo pls contact us
Hey, this isn’t Let’s Drown Out!
the volume of the video is too low....A company like Texas Instruments should do better
Bach kos bona
Too technical.
worst in explanation