In an open loop op-amp circuit, there is no concept of 'virtual ground'. However, in an op-amp with negative feedback such that it behaves as an amplifier, the inverting input maintains exact potential as that of the non-inverting input.
Very good information and excellent presentation style. I have one query... How do choose the specifications of the error amplifier? I mean how to budget the bandwidth and gain for the error amplifier?
Error amplifier gain is calculated based on your output voltage accuracy reqd. Bandwidth requirements of the amplifier depends on overall stability of the LDO and response time of the LDO..hope this helps
Hi sir. I have two questions. 1) How do you calculate the W/L ratio accurately of Pmos pass fet for a specific load current. 2) What is the main contributor to set the output voltage, error amplifier or resistor divider?
1. Decide whether you need passfet in saturation or linear. Generally saturation so that we get gain. Keep L min. Now u know current, vds, kp... So calculation is straight fw... 2. U can use both. When you change the reference voltage, output voltage will change accordingly. The error amp should have that input voltage dynamic range. But to get voltage reference which varies linearly is difficult. Resistor divider should have resistor bank to program the output voltage. Here the quiescent current will change when feedback resistor value changes. Hope its clear..
Great video sir, i had one doubt , in nmos LDO when vref and feedback voltage is same the output of opamp becomes 0 and vgs is either 0 or -ve depending on the predefined voltage at output. So will there be any offset output voltage added just to turn on the NMOS. Correct me if i went wrong anywhere.
in NMOS LDO when vref and vout are same; 1. resistor divider is not required. 2. The output of the opamp should be greater than output voltage by one Vth. suppose, Vout=1.25V, (equal to Vref), then the output of Opamp should be Vout+Vth of NMOS; i.e. 1.25+1V (assuming Vth of NMOS=1V). Hope this clarifies.
@@analoglayoutdesign2342 ,thanks sir that was very insightful. Sorry for the bad format of question formation. My question being reiterate 1)when vref=vfedback (considering virtual short) the opamp output to gate of nmos would be 0. Since for nmos vgs to be positive , won't the nmos be turned off?.
Ok if vref and vout are equal, then a.c or small signal output of opamp will be zero. But large signal or DC levels will still be maintained by opamp output. Hope I answered.
That’s true. NMOS pass element when used with lesser difference between Vin and Vout, they use a charge pump to boost the supply of the amplifier driving the pass element.
At the center of the screen is represented a n channel depletion mosfet wired in the wrong way ! After some search over internet because I didn't understand your schema, I find out that what is really in place here, is a p channel enhancement mosfet. This makes much more sense, therefore I doubt that you really understand the fundamentals of electronics.
Today cmos designs are done with enhancement devices.. and ppl shout if they use depletion mode or native NMOS devices.. yes.. symbol is edited.. but also listen to what is being told over the video…. Here the discussion is not about device understanding or device physics..
So if I understand properly, there are no oscillations in schematic simulations but after layout and parasitic extraction you are facing stability issues.. It's very difficult to point out without knowing more about ldo: architecture, current, compensation etc..
Hello sir, In nMOS LDO case i have some concerns that i have learned that nMOS works in saturation mode when Vds>Vgs-Vt. In your example, Vds=3.3-2.5>3.5-2.5-1. It seems like LDO still works with Vdd=3.3 in case Vg is not greater than 4.3. If I have any mistake, please correct me.
In NMOS LdO, NMOS stage is in common drain configuration. Let’s say vin=3.3, vout=2.5 and Vt=1v , then gate voltage should be vout+vt at least I.e. 2.5+1=3.5 Question now is where do I get 3.5v which is higher than supply of 3.3v…vin and Vdd are same…
Hi, in the slides I will not put in full information. I will write on it and explain. So please go thru the video by pausing wherever required and my suggestion is to make some notes. This is what I do when I listen to lectures. That way it will be very useful. For downloadable material, there is quite a lot of material and app notes from all product companies. That will also help.
Hello sir, thanks for the great video. Got 2 questions: 1. if Vin-Vout = V drop_out, at 35:43, V drop_out is 10-3.3=6.7V, then how come the drop out voltage is 3.6V, and later it becomes 3.6-3.3=0.3V? which one is the real drop out voltage? 2. Why when Vin is under 3.6V, the error amp won't work? Looking forward for the reply. Thank you
When the current increases suddenly, the pass element cannot provide so much current. Current is provided by load capacitor. When charge(current) is removed from Capacitor, it's voltage reduces.. which is nothing but output voltage... hope this answers
In an open loop op-amp circuit, there is no concept of 'virtual ground'. However, in an op-amp with negative feedback such that it behaves as an amplifier, the inverting input maintains exact potential as that of the non-inverting input.
The best LDO video I've ever seen.
Thanks for feedback
Excellent professor. Thanks a lot. I had watched ESD series on this channel long back
Thanks
This is really an excellent video, and channel. I can't wait to explore more of your content, sir. Thanks!
Thanks for explaining this concept in a lucid way.
Thank you SIr for nice explanation. Keep posting such circuits in analog
Thnks for helping me to recollect all my things clearly and neat and make me confident for the interview ❤️❤️❤️
Nicely explained, focussing on the major critical design parameters.
Learned a lot in short time. Thank you!
Thank you... good explanation even an ME like me can understand
I appreciate your LDO explanation.
Glad to hear it!
Excelente 👌 explicación 👍 gracias ingeniero.
Thanks for the feedback
Clear explanation .Thank you ❤
You're welcome 😊
Very good information and excellent presentation style. I have one query... How do choose the specifications of the error amplifier? I mean how to budget the bandwidth and gain for the error amplifier?
Error amplifier gain is calculated based on your output voltage accuracy reqd. Bandwidth requirements of the amplifier depends on overall stability of the LDO and response time of the LDO..hope this helps
Nice explain sir.many many thanks sir👌👌👌👌👌👌👌👌👌👌👌👌👌👌
I have a doubt. How Error amplifier can be used with positive feedback? As far as I know any amplifier works with negative feedback.
Good Explanation Sir :)
Hi sir.
I have two questions.
1) How do you calculate the W/L ratio accurately of Pmos pass fet for a specific load current.
2) What is the main contributor to set the output voltage, error amplifier or resistor divider?
1. Decide whether you need passfet in saturation or linear. Generally saturation so that we get gain. Keep L min. Now u know current, vds, kp... So calculation is straight fw...
2. U can use both.
When you change the reference voltage, output voltage will change accordingly. The error amp should have that input voltage dynamic range. But to get voltage reference which varies linearly is difficult.
Resistor divider should have resistor bank to program the output voltage. Here the quiescent current will change when feedback resistor value changes.
Hope its clear..
@@analoglayoutdesign2342 Ok sir. Thank you.
Thank you sir, nice explanation
Very nicely explained..
Great video sir, i had one doubt , in nmos LDO when vref and feedback voltage is same the output of opamp becomes 0 and vgs is either 0 or -ve depending on the predefined voltage at output. So will there be any offset output voltage added just to turn on the NMOS. Correct me if i went wrong anywhere.
in NMOS LDO when vref and vout are same;
1. resistor divider is not required.
2. The output of the opamp should be greater than output voltage by one Vth. suppose, Vout=1.25V, (equal to Vref), then the output of Opamp should be Vout+Vth of NMOS; i.e. 1.25+1V (assuming Vth of NMOS=1V). Hope this clarifies.
@@analoglayoutdesign2342 ,thanks sir that was very insightful. Sorry for the bad format of question formation.
My question being reiterate
1)when vref=vfedback (considering virtual short) the opamp output to gate of nmos would be 0. Since for nmos vgs to be positive , won't the nmos be turned off?.
Ok if vref and vout are equal, then a.c or small signal output of opamp will be zero. But large signal or DC levels will still be maintained by opamp output. Hope I answered.
@@analoglayoutdesign2342 , great sir , yeah it's clarified now
But giving 5 voltage and having 2.5 voltage, There will be a so much drop using NMOS pass element
That’s true. NMOS pass element when used with lesser difference between Vin and Vout, they use a charge pump to boost the supply of the amplifier driving the pass element.
agreed, good job
Nicely explained 👍👍
At the center of the screen is represented a n channel depletion mosfet wired in the wrong way !
After some search over internet because I didn't understand your schema, I find out that what is really in place here, is a p channel enhancement mosfet. This makes much more sense, therefore I doubt that you really understand the fundamentals of electronics.
Today cmos designs are done with enhancement devices.. and ppl shout if they use depletion mode or native NMOS devices.. yes.. symbol is edited.. but also listen to what is being told over the video…. Here the discussion is not about device understanding or device physics..
I am looking more videos from you..........
Sir,Can you a video on pole zero compensation . There is no video telling practical approach on this topic anywhere.
Ok. Will upload one video on ldo compensation
@@analoglayoutdesign2342 yes sir, it would help greatly.
Superb sir
Great content,
Thanks for the feedback
When we get oscillations at the output of the LDO what is suggested to be changed first and subsequently from layout perspective?
So if I understand properly, there are no oscillations in schematic simulations but after layout and parasitic extraction you are facing stability issues..
It's very difficult to point out without knowing more about ldo: architecture, current, compensation etc..
Nice explain
Thanks
Hello sir,
In nMOS LDO case i have some concerns that i have learned that nMOS works in saturation mode when Vds>Vgs-Vt. In your example, Vds=3.3-2.5>3.5-2.5-1. It seems like LDO still works with Vdd=3.3 in case Vg is not greater than 4.3. If I have any mistake, please correct me.
In NMOS LdO, NMOS stage is in common drain configuration. Let’s say vin=3.3, vout=2.5 and Vt=1v , then gate voltage should be vout+vt at least I.e. 2.5+1=3.5
Question now is where do I get 3.5v which is higher than supply of 3.3v…vin and Vdd are same…
Hope this answers your question
Very nice talk, do you share your slides as well? Are they downloadable ?
Hi, in the slides I will not put in full information. I will write on it and explain. So please go thru the video by pausing wherever required and my suggestion is to make some notes. This is what I do when I listen to lectures. That way it will be very useful.
For downloadable material, there is quite a lot of material and app notes from all product companies. That will also help.
Thanks for the feedback. If you have further questions, please post it in the comments section. Thanks
Hello sir, thanks for the great video.
Got 2 questions:
1. if Vin-Vout = V drop_out, at 35:43, V drop_out is 10-3.3=6.7V, then how come the drop out voltage is 3.6V, and later it becomes 3.6-3.3=0.3V?
which one is the real drop out voltage?
2. Why when Vin is under 3.6V, the error amp won't work?
Looking forward for the reply. Thank you
Drop out voltage is the minimum voltage between Vin and vout after which regulation stops.
Regulation stops bcos the Vin and vout difference is so less that pass element becomes a simple series resistor between Vin and vout
@@analoglayoutdesign2342 Thank you sir, you mean the pass element is similar to diode connection?
@@vectorhehe7905 no.. it's not like diode connected..it's in linear region..simple mos resistor
@@jayateerthar5224 oh you are right, I forgot this pass element here is a PMOS
so helpful tnx
Thanks for feedback
The best video 👏
Thanks for feedback
How the output voltage decreases when the load current increases suddenly
Pls explain this.
When the current increases suddenly, the pass element cannot provide so much current. Current is provided by load capacitor. When charge(current) is removed from Capacitor, it's voltage reduces.. which is nothing but output voltage... hope this answers
Understood, Thanks!!
In dropout voltage why value is =0.3?
Need not be 0.3... can be even 0.1v ...I just took an example of 0.3v
why load cap is needed in ldo? what is purpose of that load cap in ldo?
Load cap supplies instantaneous load currents. Otherwise the transient load regulation will be very bad.
@@analoglayoutdesign2342 thank you
Note: 05:30 classification PS: linear switching
Are you referring to hybrid LDO?
We have some design ideas, Sir. Would it be possible and appropriate to hire you as our advisor? How can we connect?
Please email me your contact details jt.analog@gmail.com
sir, can u explain on Rc circuits
Plan is there
Hi sir... Waiting for few more
Sure..
It's wrong you have given positive feedback to error amplofier, it should be negative feedback.
Please go thru the video.. everything is explained.. no body will explain to you by coming down to such low level of basics
1 St view
Thanks a lot sir
Sir plz upload video on PLL.
Will do
Sir when it will come
How do we derive Transfer function from VDD to VOUT?
Basically for psrr, we will do this.
We need to write down small signal equivalent ckt for that and then get the transfer function
Waiting for new videos
As soon as I get little time, I will upload...even I want to upload video...let me see how to do it quickly
@@analoglayoutdesign2342 Ok..
Hi,why we connect loads in circuits
LDO is a power supply. It can supply current to different circuits that load the power supply. Load means load current.
Please take buck , boost and buck boost concepts.....
Sure will do
17:37 I(load) or ı(leaked) ?
I load...zero to full load
28:16
Sorry, I accidentally press dislike, I'm sorry