Bro, i am saying that even my professors can't teach like you. You are a gem in teaching and i would really love the way you are making things simpler to be understood by us...Lots of Love💌💌💌
Great session! The extra detail on blocking versus non-blocking (above what the HDLbits course included) were super helpful! The examples with variables a, b, c were helpful. But what really cleared things up as to why we have these two types of assignments was the shift register example. That made it totally clear why we need both types of assignments. Thank you!
Hi , I am enjoying these verilog series. Love your teaching. It makes it total fun to check our understanding by practically writing the code at hdlbits site. Just curious to know if you would teach System verilog anytime soon as well ?
Bro, i am saying that even my professors can't teach like you. You are a gem in teaching and i would really love the way you are making things simpler to be understood by us...Lots of Love💌💌💌
Great session! The extra detail on blocking versus non-blocking (above what the HDLbits course included) were super helpful! The examples with variables a, b, c were helpful. But what really cleared things up as to why we have these two types of assignments was the shift register example. That made it totally clear why we need both types of assignments. Thank you!
Wow thanks a lot for detailed feedback… this means a lot …. Keep enlightening me once a while with such kind of detailed feedback. Thanks again ❤️
module clock_gen(output reg clock);
initial
clock = 1'b0;
always
#10 clock = ~clock;
Endmodule
Good work 😃
Good session bro.. keep it up
Hi , I am enjoying these verilog series. Love your teaching. It makes it total fun to check our understanding by practically writing the code at hdlbits site. Just curious to know if you would teach System verilog anytime soon as well ?
The third error is syntax error of always block, the always block does not have a sensitivity list