@18:58 For 2nd and 3rd example interms of code except blocking and non blocking how come circuit become different . Thus 3rd example circuit diagram's no. of flip-flop (i.e 2) same for blocking and non-blocking but same not for the 2nd example. For the answer to the question asked at the last regarding proper hardware--> In case of blocking will use continuously driven wire with and gates without storing data whereas in non-blocking code will use Latch . Please do correct me if I'm wrong.
20:39 1st always block create pure combinational logic, but the 2nd always block infers 2 latches. You previously told to avoid unwanted latches while designing combinational circuit we're using blocking statement 🤷
I understood your query. Hardwares are always parallel, they don't wait for anything because input comes continuously and already stored data are overwritten. This is the behaviour of a real hardware. Here , there is data dependency means last output depends on previous output. This kind of behaviour is very well handled by non blocking assignment than blocking assignment. This is what I meant. again, blocking and non blocking doesn't mean combinatioal and sequential logic design and wire and reg is not combinational and sequential design always. Tools generate hardware according to what we write or the rule we followed. Don't worry, many of your doubts will be cleared in my next tutorial . I will upload a tutorial on reg and wire(part-2) very soon.
PLEASE CLARIFY . For the last question in this video . The combinational logic has data dependency(anyway the final output will not come until previous statement is executed) and can be executed using blocking statements itself. What is the need for using non blocking .
The code we write must generate a hardware but there is a catch, it should not be some random hardware but the actual hardware. If the code generates actual hardware then it reduces the time of vlsi design cycle else circuit needs to be optimiszed by synthesis tool and consumes design cycle. At hardware level all the codes are executed parallely and not sequentially. It's not 100% true that one should use blocking statement for combinatioal logic only. It depends on the best possible solution to write a code to get a optimised hardware. The one, writing code sould be sure what exactly he or she is doing rather than simply following some rule. I am not sure whether you understood my points or not. I know, I didn't give your answer directly but this is the answer. Thanks.
@@ComponentByte if we use non blocking assignment for combinational logic ,we will face latch up condition ,which is not desirable for combinational logic ,then why are you suggesting non blocking assignments for combinational logic ?
I have never suggested non blocking assignment for combinational design. But what I have said is non blocking assignment doesn't generate always a combinational logic. Writing code is not about generating hardware but an accurate hardware that is optimized interms of timing and area. What I mean is use whatever you want but it should generate intended hardware.
Sir if we want to design an asynchronous sequential counter , then in that case we will use always@(posedge) with the blocking assignment as this is the ripple counter , please clarify my doubt??
The best practice to write verilog code is to draw the logic diagram. Then write code for it. First, design single module whether it's dff or any other and then instantiate it as many time as you want. For DFF you will have always@(posedge clk or posedge rst) ........... assign is always used with blocking assignment operator (Yes you are correct)
@@ComponentByte sir what is the difference between these two statements - assign a = b+c; And a = b+c; In the first code we are using continuous datatype at LHS but in the second line of code we have register type at LHS but both are storing the a+b, so what's the difference??
assign a = b+c Here ,whenever b or c value changes a is updated to new value. a = b+c This statement must be within always() block Then value of a is updated whenever the parameters inside paranthesis changes
Yes, definitely i can. But i don't have a proper set up to make all these tutorial means whether I should use pen paper writing digital pen and tab writing . It matters a lot because these course requires lot of writing. Then again how to capture all these tutorials (camera) In my verilog tutorial i write very less so it's manageable but for some other b.tech level tutorial, writing and explanation is must. I just can't type and explain. Again, whether tutorial should be in English or Hindi. English, i am Ok but not that great Hindi , i am comfortable but as it's not my native language so Grammatical error will always be there but I can explain concepts in Hindi far better than English language. I have a job also. So time has to permit. Lot of confusion 🤔 Let me find the best solution.
I have a net that the host writes to, however when it reads back from the register, I'd like to replace the lsb with a status generated in the logic. i.e. ctrl_reg[0]
@18:58 For 2nd and 3rd example interms of code except blocking and non blocking how come circuit become different . Thus 3rd example circuit diagram's no. of flip-flop (i.e 2) same for blocking and non-blocking but same not for the 2nd example.
For the answer to the question asked at the last regarding proper hardware-->
In case of blocking will use continuously driven wire with and gates without storing data whereas in non-blocking code will use Latch . Please do correct me if I'm wrong.
same doubt arrised for me
20:39 1st always block create pure combinational logic, but the 2nd always block infers 2 latches. You previously told to avoid unwanted latches while designing combinational circuit we're using blocking statement 🤷
I understood your query.
Hardwares are always parallel, they don't wait for anything because input comes continuously and already stored data are overwritten. This is the behaviour of a real hardware.
Here , there is data dependency means last output depends on previous output. This kind of behaviour is very well handled by non blocking assignment than blocking assignment. This is what I meant.
again, blocking and non blocking doesn't mean combinatioal and sequential logic design and wire and reg is not combinational and sequential design always. Tools generate hardware according to what we write or the rule we followed.
Don't worry, many of your doubts will be cleared in my next tutorial .
I will upload a tutorial on reg and wire(part-2) very soon.
PLEASE CLARIFY .
For the last question in this video . The combinational logic has data dependency(anyway the final output will not come until previous statement is executed) and can be executed using blocking statements itself. What is the need for using non blocking .
The code we write must generate a hardware but there is a catch, it should not be some random hardware but the actual hardware. If the code generates actual hardware then it reduces the time of vlsi design cycle else circuit needs to be optimiszed by synthesis tool and consumes design cycle.
At hardware level all the codes are executed parallely and not sequentially. It's not 100% true that one should use blocking statement for combinatioal logic only. It depends on the best possible solution to write a code to get a optimised hardware. The one, writing code sould be sure what exactly he or she is doing rather than simply following some rule.
I am not sure whether you understood my points or not. I know, I didn't give your answer directly but this is the answer.
Thanks.
@@ComponentByte if we use non blocking assignment for combinational logic ,we will face latch up condition ,which is not desirable for combinational logic ,then why are you suggesting non blocking assignments for combinational logic ?
I have never suggested non blocking assignment for combinational design. But what I have said is non blocking assignment doesn't generate always a combinational logic. Writing code is not about generating hardware but an accurate hardware that is optimized interms of timing and area.
What I mean is use whatever you want but it should generate intended hardware.
Sir if we want to design an asynchronous sequential counter , then in that case we will use always@(posedge) with the blocking assignment as this is the ripple counter , please clarify my doubt??
The best practice to write verilog code is to draw the logic diagram. Then write code for it.
First, design single module whether it's dff or any other and then instantiate it as many time as you want.
For DFF you will have
always@(posedge clk or posedge rst)
...........
assign
is always used with blocking assignment operator (Yes you are correct)
@@ComponentByte sir what is the difference between these two statements -
assign a = b+c;
And
a = b+c;
In the first code we are using continuous datatype at LHS but in the second line of code we have register type at LHS but both are storing the a+b, so what's the difference??
assign a = b+c
Here ,whenever b or c value changes a is updated to new value.
a = b+c
This statement must be within always() block
Then value of a is updated whenever the parameters inside paranthesis changes
Good explanation,but would have been good if explained in hindi.
Sir can you explain electricity chapter please sir please
Yes, definitely i can.
But i don't have a proper set up to make all these tutorial means whether I should use
pen paper writing
digital pen and tab writing .
It matters a lot because these course requires lot of writing.
Then again how to capture all these tutorials (camera)
In my verilog tutorial i write very less so it's manageable but for some other b.tech level tutorial, writing and explanation is must. I just can't type and explain.
Again, whether tutorial should be in English or Hindi.
English, i am Ok but not that great Hindi , i am comfortable but as it's not my native language so Grammatical error will always be there but I can explain concepts in Hindi far better than English language.
I have a job also. So time has to permit.
Lot of confusion 🤔
Let me find the best solution.
Ok sir
Sir thats means when you start this
Because I study in class 10
Sir if possible please explain router project
There is a project named switch in testbench.in
Check once if it helps.
Because I have no such content with me.
I have a net that the host writes to, however when it reads back from the register, I'd like to replace the lsb with a status generated in the logic. i.e.
ctrl_reg[0]
I didn't get your query.