How can the setup and hold time be negative ??

Поділитися
Вставка
  • Опубліковано 23 гру 2024

КОМЕНТАРІ •

  • @kamleshraiter658
    @kamleshraiter658 3 роки тому +8

    This is probably a misconception. Hold and setup time are property of flip-flop and they remain fixed and can't be changed. The only thing that is changing is the timing equations values due delays, clock to Q and clock skew

  • @TheGreatShawnY
    @TheGreatShawnY 4 роки тому

    Thanks for your effort of explaining! Merry Christmas and Happy New Year!

  • @muggullasairam8442
    @muggullasairam8442 3 місяці тому +1

    Before watching this video i suggest go through internal circuit for a flop.

  • @mukulsharma8616
    @mukulsharma8616 4 роки тому +1

    Will you please make a video on concept of pipeline in RTL Design, thanks and keep up the good work 👍

  • @rockingstone7700
    @rockingstone7700 3 роки тому

    Sir when delay is being provided to clock then why it is shifted left in timing diagram.... It should be shifted towards right.... Plz clarify this

    • @messiweltmeista
      @messiweltmeista 3 роки тому +1

      I was thinking exact the same thing. When the clock input is delayed, it should come later, not earlier

    • @GregoriousApartment
      @GregoriousApartment 2 роки тому

      see notations carefully

    • @rockingstone7700
      @rockingstone7700 2 роки тому

      @@GregoriousApartment I have watched thoroughly if u have understood then atleast tell the crux behind it ....hope u under my question what I have asked

    • @alvinaug3844
      @alvinaug3844 7 місяців тому

      Yes, same I also think

  • @meenugarg1102
    @meenugarg1102 4 роки тому

    Nice explanation

  • @faneeshbansal
    @faneeshbansal Рік тому

    Sir hold time can be negative but setup time will always be positive