Negative Setup time and Hold time || STA 10

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  • Опубліковано 23 гру 2024

КОМЕНТАРІ • 3

  • @shreyajha2794
    @shreyajha2794 9 місяців тому +2

    Hello sir I preparing for VEDA IIT entrance exam for analog engineering. Mains exam date is 16 March but I have only prepared upto MOSFET small signal common source amplifier and I haven't prepared for amplifier op apms MOS cascode and current mirror. Sir, I also have to look on to Network analysis(questions on RLC, RMS, complex circuit, sinusoidal voltage). Sir, I don't know what to do sir please guide me. As this exam is very important to me. I really don't have such money to get a training in VLSI, so I really want to clear this exam.

    • @knowledgeunlimited
      @knowledgeunlimited  9 місяців тому

      Current mirror circuits are important.
      But since you were saying you didn’t covered fully, go with confidence on what all concepts you are familiar with and be genuine with Interviewer. All we can do is to hope for best.
      Best of the luck with the process.

  • @keshavbaldeva5438
    @keshavbaldeva5438 6 місяців тому

    setup time can not be negative🙃