For those who wondering why LOW signal of CLR was chosen for activation - there’s an inverter behind CLR input in actual circuits, so LOW internally becomes HIGH (in some cases CLK might also be inverted) 🤷🏻♂️
Ahsan Niaz there is no function. There are modules in verilog and they are way different than functions. And also you can not call module inside of any procedure. It should be always outside. To be more clear you can not call any module inside @always block
Please help... + seal3081 I am a little confused about the asynchronous clear if ( !clr ) { } and if ( clr == 0 ) { } Have the same meaning ? i mean clr is zero in both cases , !clr = 0?
Antreas Apostolou It is asynchronous because of the statement negedge Clr_ in the sensitivity list. That means that the always block is executed not only at the positive edge of the clock, but also at the negative edge of Clr_, whenever this may occur (asynchronous with respect to clk).
For those who wondering why LOW signal of CLR was chosen for activation - there’s an inverter behind CLR input in actual circuits, so LOW internally becomes HIGH (in some cases CLK might also be inverted) 🤷🏻♂️
oh man you just saved my lab. thank you
What is the code of asynchronous down counters in Verilog programming (EDA playground compiler)?
Plz help
You know this answer or not bro
Tell me plzz
No
I searched on the Internet and no solution if you have it pls send it
Good work!, thank you sir
cảm ơn bác
can u please make a playlist for verilog??
very helpful
Can you explain why we use
erq non block ing statement
look up why this is, but you always want to use
just what i needed, thanks
Sir can we use else if?like
if(....)
{
function
}
else if(.....)
{
function
}
Ahsan Niaz there is no function. There are modules in verilog and they are way different than functions. And also you can not call module inside of any procedure. It should be always outside. To be more clear you can not call any module inside @always block
Please help... + seal3081
I am a little confused about the asynchronous clear
if ( !clr ) { }
and
if ( clr == 0 ) { }
Have the same meaning ? i mean clr is zero in both cases , !clr = 0?
Antreas Apostolou It is asynchronous because of the statement negedge Clr_ in the sensitivity list. That means that the always block is executed not only at the positive edge of the clock, but also at the negative edge of Clr_, whenever this may occur (asynchronous with respect to clk).
Peter Mathys
Yes i can understand, but what about the !CLR value...is it zero ?
hello and thank you old man. can i have the text material