Verilog for Registers and Counters

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  • Опубліковано 24 гру 2024

КОМЕНТАРІ • 21

  • @VRchitecture
    @VRchitecture Рік тому

    For those who wondering why LOW signal of CLR was chosen for activation - there’s an inverter behind CLR input in actual circuits, so LOW internally becomes HIGH (in some cases CLK might also be inverted) 🤷🏻‍♂️

  • @andrewpersaud4144
    @andrewpersaud4144 7 років тому +2

    oh man you just saved my lab. thank you

  • @yazanabdalrazak9647
    @yazanabdalrazak9647 4 роки тому +1

    What is the code of asynchronous down counters in Verilog programming (EDA playground compiler)?
    Plz help

  • @ቁምነገርቲዩብ-ቘ9ከ
    @ቁምነገርቲዩብ-ቘ9ከ 6 років тому

    Good work!, thank you sir

  • @lethanhcan5544
    @lethanhcan5544 9 років тому

    cảm ơn bác

  • @ramkaranverma8862
    @ramkaranverma8862 4 роки тому +1

    can u please make a playlist for verilog??

  • @ParasSachapara1212
    @ParasSachapara1212 9 років тому +1

    very helpful

  • @alwayserik
    @alwayserik 8 років тому +2

    Can you explain why we use

    • @imharsha2259
      @imharsha2259 7 років тому

      erq non block ing statement

    • @danntraz
      @danntraz 5 років тому

      look up why this is, but you always want to use

  • @seal3081
    @seal3081 10 років тому

    just what i needed, thanks

  • @ahsanniaz8282
    @ahsanniaz8282 7 років тому

    Sir can we use else if?like
    if(....)
    {
    function
    }
    else if(.....)
    {
    function
    }

    • @yasinfatullayev
      @yasinfatullayev 5 років тому

      Ahsan Niaz there is no function. There are modules in verilog and they are way different than functions. And also you can not call module inside of any procedure. It should be always outside. To be more clear you can not call any module inside @always block

  • @antreasapostolou2019
    @antreasapostolou2019 9 років тому

    Please help... + seal3081
    I am a little confused about the asynchronous clear
    if ( !clr ) { }
    and
    if ( clr == 0 ) { }
    Have the same meaning ? i mean clr is zero in both cases , !clr = 0?

    • @mathys2000yt
      @mathys2000yt  9 років тому +1

      Antreas Apostolou It is asynchronous because of the statement negedge Clr_ in the sensitivity list. That means that the always block is executed not only at the positive edge of the clock, but also at the negative edge of Clr_, whenever this may occur (asynchronous with respect to clk).

    • @antreasapostolou2019
      @antreasapostolou2019 9 років тому

      Peter Mathys
      Yes i can understand, but what about the !CLR value...is it zero ?

  • @bediosoro7786
    @bediosoro7786 6 років тому

    hello and thank you old man. can i have the text material