at 20.34 , clr =1 is applied after 7 (2+5), not at the edge of clk
Well explained. Thank you ;)
In the last test bench of adder circuit what is the effect of myseed=15 ? Means what will be the effect of value 15 here?
Hello , at 31:54 what will be the difference if myseed = 10?
At 26:15 example 3 In always statement you forget to mention "begin...... end".
Yes you are right.. Thanks
Good morning sir.How to write a self checking test bench for arithmetic operators
Well explained. Thank u sir :)
was that the DataFlow model? sir have mentioned it as behavioral at 2:12
Its data flow...
It's data flow modelling
which lecture contains syntax and basics of writing a verilog test bench
21
This was too much to engulf
at 20.34 , clr =1 is applied after 7 (2+5), not at the edge of clk
Well explained. Thank you ;)
In the last test bench of adder circuit what is the effect of myseed=15 ? Means what will be the effect of value 15 here?
Hello , at 31:54 what will be the difference if myseed = 10?
At 26:15 example 3
In always statement you forget to mention "begin...... end".
Yes you are right.. Thanks
Good morning sir.
How to write a self checking test bench for arithmetic operators
Well explained. Thank u sir :)
was that the DataFlow model? sir have mentioned it as behavioral at 2:12
Its data flow...
It's data flow modelling
which lecture contains syntax and basics of writing a verilog test bench
21
This was too much to engulf