WRITING VERILOG TEST BENCHES

[@sanjeevyadav-lw4ky]

at 20.34 , clr =1 is applied after 7 (2+5), not at the edge of clk

[@harihara.t]

Hello , at 31:54 what will be the difference if myseed = 10?

[@aminl1812]

Well explained. Thank you ;)

[@sahelighosh4297]

In the last test bench of adder circuit what is the effect of myseed=15 ? Means what will be the effect of value 15 here?

[@cipherswami]

was that the DataFlow model? sir have mentioned it as behavioral at 2:12

[@prajwal4245]

Its data flow...

[@kotreshick1845]

It's data flow modelling

[@xenderlive4865]

At 26:15 example 3
In always statement you forget to mention "begin...... end".

[@reguideu2266]

Yes you are right.. Thanks

[@pavimahi4501]

Good morning sir.
How to write a self checking test bench for arithmetic operators

[@SurajitDas-gk1uv]

Well explained. Thank u sir :)

[@shwetharani9019]

which lecture contains syntax and basics of writing a verilog test bench

[@prajwal4245]

21

[@xcommandergaming5949]

This was too much to engulf