When i see someone Indian I'm directly going to watch the video. Because you really help us and u are the best in all the majors. Thank u so much and appreciate ur help.
I suggest to completely rework this and split into at least two lectures and add more examples. I felt rushed and confused and till this point I was constantly ahead in your lectures.
The first time I watched this, it didn't make complete sense to me, but after watching some other videos it made perfect sense and I understood it completely. The videos are from the playlist and I will mention them down below for others struggling with the same thing: Analysis of Clocked Sequential Circuits (with D Flip Flop) Analysis of Clocked Sequential Circuits (with JK Flip Flop) Analysis of Clocked Sequential Circuits (with T Flip Flop) State Reduction and Assignment
@@QazWsx-sn3bn you can use any type of flip flop .... Generally D and T flip flops are used because they are comapritively easier and require less equations than JK flip flop
To all those wondering about step 6 No specific reason for using T flip flop. Implementation using D flip flop is easy because next state is same as data input and implementation using JK flip flop takes time, maybe that's why i used T.
Most of time It's given using which flip-flop we have to design a Circuit, and if it's not mentioned go for D flip-flop because it's easy to design circuit using that.
00:05 Learn how to design clocked sequential circuits in 9 steps 02:30 State table filled for input 0 and 1 04:53 States cannot be reduced further 07:09 Determining the number of flip flops required and assigning letter symbols 09:19 Derive circuit excitation table from state table 12:01 Implementing a circuit using T flip flop 14:22 Implementing an excitation table for a circuit 00:03 Nine steps for implementing clocked sequential circuits Crafted by Merlin AI.
man, even tho you skipped number 6 which is just a trivial step based on the question, this is amazing you put high quality content like this that will go a long way for students. you deserve an award of some sort, some level of recognition for your contributions outside of youtube comment section on your own videos. keep up the revolutionary work.
+NesoAcademy Output(y) should be a function of (x,Qa+,Qb+) at17:30 because the moment x takes it desired value and clock pulse occurs value of Qa and Qb will be changed to Qa+ and Qb+.
I was wondering the same thing. I tried making y a function of x and the next states, and it ended with the correct result. However this leads me to ask. Since this is a Mealy machine, does the output change asynchronously? When I toggle the input values for it, the output changes irrespective of the clock. Is this behavior typical in mealy machines?
The state diagrams discussed in this video remind me of Caley diagrams used in group theory. A group is the fundamental object in the study of abstract algebra. We can construct a group by first identifying a set of elements. We then form all possible permutations of this set, and assign a unique symbol to each permutation. The collection of symbols representing permutations is called a group if there exists a rule for composing any two elements of the group. The rule must follow a few axioms, but this information is not necessary for you to understand my point. The behavior of a group can be summarized in two ways. We may create a composition table or a Caley diagram. The composition table looks exactly like the multiplication table we all grew up memorizing in elementary school. The Caley diagram looks EXACTLY like the state diagrams used to describe the behavior of a sequential circuit. In fact, I am 100% sure that the state diagram in this video could be used to describe the behavior of a group in abstract algebra. My conjecture is that there is a structure preserving relationship (isomorphism) between state diagrams and Caley diagrams. I find this idea extremely tantalizing because it establishes an intimate and fundamental relationship between computer science and abstract algebra. I wonder if this idea might be extended to conclude that there exists a group (field, ring, vector space, or some combination of all four) that perfectly represents the behavior of a computer's CPU, ALU, or the whole machine.
point 6 is missing great job sir keep it up i will join you soon as i am currently busy in study i will be a part of you free and provide the lectures as much as i can
hello @nesoacademy ,im very thankful to you for your efforts and would like you to know that a lot of people are pirating your videos and uploading them onyoutube.plz report them
@@wish_one_knot5006 I'd say JK if the two inputs are independent, D if the two inputs are always equal or you have only 1 input, T if you need Q to be complemented for each clock cycle.
Thanks for these amazing lectures! I have just one question - Can't we evaluate equations for next state and then implement them through Flip Flops. Like can't we write QA+ in terms of QA, QB and x, solve them through k-map, do the same for QB+ and then implement the circuit?
@@nannubedi7773 Yes, you are correct. In digital circuit design, it is common to first write the Boolean equations for the next state of a flip-flop or sequential circuit and then implement the circuit using logic gates and flip-flops. One approach to implementing a sequential circuit is to write the Boolean equations for the next state of each flip-flop in terms of the current state of the flip-flops and the input signals. These equations can then be simplified using Boolean algebra or Karnaugh maps to obtain a minimized form. The minimized equations can be implemented using logic gates and flip-flops. For example, suppose we have a sequential circuit with two flip-flops, QA and QB, and an input signal x. We want to design a circuit that computes the next state of the flip-flops, QA+ and QB+, based on the current state and input signal. We can write the Boolean equations for the next state as: QA+ = f(QA, QB, x) QB+ = g(QA, QB, x) where f and g are Boolean functions. We can then simplify these equations using Karnaugh maps or Boolean algebra to obtain a minimized form. The minimized equations can be implemented using logic gates and flip-flops. So, to answer your question, yes, you can evaluate the equations for the next state and then implement them using flip-flops and logic gates. This approach is commonly used in digital circuit design.
You can use any flipflop honestly... As long as you know how that flipflop works and you know it's truth table, you can make it's excitation table and find the expressions... The rest is just simply implementing the circuit
@nesoacademy Sir, at 6:33 you are explaining that state reduction is not possible for the state table that has been obtained. For P.S. {0,0} and for x=1 as input, N.S. is {0,1}. Also, for P.S. {0,1} and for x=1 as input, the N.S. is again {0,1}. So, the N.S. {0,1} is repeated. Moreover, for both of these rows the output y is the same and equal to zero (y=0 under the x=1 column). Hence, state reduction is possible as there is a valid repetition in the state table. Sir can you please tell the procedure for performing the state reduction in the above mentioned case.
@@Aryan_agarwal830 but i found the answer to it . state reduction can only happen when the states have next state and output same for all values of input x s0 and s1 have same output and next state but only at s0 x=1 and s1 x=0 which is different input so no state reduction can be done
Hello sir, first of all, thank you for your excellent lectures. But I've a question.... You've said on 13:56 that you are making the characteristic table for T-FF. But my ques is.. is this the characteristic table or the excitation table of T-FF?
these lectures are really god but one thing that i have to tell you that if any lecture is related to the another one then please mention that lecture number so we can easily go through that lecture and learn that i left.
These lectures are very helpful..Thank you so much neso academy..but I have a doubt..In my examination only input and outputs were given..so how to determine the state diagram from input and output..if anyone know that please comment here.. the input is=110101 and the output is=010100. so from this how to determine the state diagram??
sir first of all a very thanking you for this video. My question is that if i have 5 states then in this case which flip flap can i use for implementation of circuit......please give the answer...!!
How do you know there will be 2 state variables in the first step??? I think you looked at the state transition diagram for that, but sometimes there is only verbal description of the problem, not diagram. How do we know the number of state variables? Or is it directly related to number of states? If there is 4 state, then only 2 state variables. If there are 5 to 8 states, then 3 state variables. Is that so?
its not redundant because in both the cases NS is different for x = 1 and the output is different too. two states are redundant only if the next state as well as output is completely same
hi. If u can help me the first two steps. A car has different light states on its head and taillight. For break,for normal light, for turning left, for turning right, and the other is for hazard. Design a state machine that controls these state for the car headlight and taillight.
I have a doubt regarding step 3 why reduction is not possible because for present state 0,0 and 0,1 the next state same 0,1 and output same 0,0 (for x = 1)
I think lecture are too slow for the students who already know the concepts and only watching these videos for revision . Apart from this the whole series is very good and we can learn all the thing here from basics .
![[COA 40] Sequential circuit design using JK Flip flops (State diagram, excitation tables), KA = BX'](/img/n.gif)
When i see someone Indian I'm directly going to watch the video. Because you really help us and u are the best in all the majors. Thank u so much and appreciate ur help.
I suggest to completely rework this and split into at least two lectures and add more examples. I felt rushed and confused and till this point I was constantly ahead in your lectures.
The first time I watched this, it didn't make complete sense to me, but after watching some other videos it made perfect sense and I understood it completely. The videos are from the playlist and I will mention them down below for others struggling with the same thing:
Analysis of Clocked Sequential Circuits (with D Flip Flop)
Analysis of Clocked Sequential Circuits (with JK Flip Flop)
Analysis of Clocked Sequential Circuits (with T Flip Flop)
State Reduction and Assignment
god bless
Can you explain to me point no 6?
@@QazWsx-sn3bn you can use any type of flip flop .... Generally D and T flip flops are used because they are comapritively easier and require less equations than JK flip flop
To all those wondering about step 6
No specific reason for using T flip flop. Implementation using D flip flop is easy because next state is same as data input and implementation using JK flip flop takes time, maybe that's why i used T.
You're right 👍
5:13
6:45 no state redn
8:04 state assignment
9:25 no of flipflops
15:54 circuit excitation table
18:07 expression
sir didnt tell us how to decide type of flip flop
padhle bhai ye sab mat kar
@@deepakkumarsingh4571 We can implement it with any FF's its our choice ..
no there is different in definition@@ChabPoha
Most of time It's given using which flip-flop we have to design a Circuit, and if it's not mentioned go for D flip-flop because it's easy to design circuit using that.
Thank you sir. Will follow
Thanks
Thank you very much for all the time and effort that you put into making these lectures!
Hassan Alshehri ki
You're my life saver. Thank you so much. Your efforts shall never go unrecognized. I am truly grateful for your existence.
00:05 Learn how to design clocked sequential circuits in 9 steps
02:30 State table filled for input 0 and 1
04:53 States cannot be reduced further
07:09 Determining the number of flip flops required and assigning letter symbols
09:19 Derive circuit excitation table from state table
12:01 Implementing a circuit using T flip flop
14:22 Implementing an excitation table for a circuit
00:03 Nine steps for implementing clocked sequential circuits
Crafted by Merlin AI.
you are very smart teacher , direct to the point , no unnecessary info
thanks a lot just seen 30 minutes before my exam and performed well
last min big god
man, even tho you skipped number 6 which is just a trivial step based on the question, this is amazing you put high quality content like this that will go a long way for students. you deserve an award of some sort, some level of recognition for your contributions outside of youtube comment section on your own videos. keep up the revolutionary work.
How can u decide that t flip-flop
@@hondahonda1539Yeah I too didn't get that
+NesoAcademy Output(y) should be a function of (x,Qa+,Qb+) at17:30 because the moment x takes it desired value and clock pulse occurs value of Qa and Qb will be changed to Qa+ and Qb+.
I was wondering the same thing. I tried making y a function of x and the next states, and it ended with the correct result.
However this leads me to ask. Since this is a Mealy machine, does the output change asynchronously? When I toggle the input values for it, the output changes irrespective of the clock. Is this behavior typical in mealy machines?
The state diagrams discussed in this video remind me of Caley diagrams used in group theory. A group is the fundamental object in the study of abstract algebra. We can construct a group by first identifying a set of elements. We then form all possible permutations of this set, and assign a unique symbol to each permutation. The collection of symbols representing permutations is called a group if there exists a rule for composing any two elements of the group. The rule must follow a few axioms, but this information is not necessary for you to understand my point.
The behavior of a group can be summarized in two ways. We may create a composition table or a Caley diagram. The composition table looks exactly like the multiplication table we all grew up memorizing in elementary school. The Caley diagram looks EXACTLY like the state diagrams used to describe the behavior of a sequential circuit. In fact, I am 100% sure that the state diagram in this video could be used to describe the behavior of a group in abstract algebra.
My conjecture is that there is a structure preserving relationship (isomorphism) between state diagrams and Caley diagrams. I find this idea extremely tantalizing because it establishes an intimate and fundamental relationship between computer science and abstract algebra. I wonder if this idea might be extended to conclude that there exists a group (field, ring, vector space, or some combination of all four) that perfectly represents the behavior of a computer's CPU, ALU, or the whole machine.
Thank u sir its very helpful for my final exam
How did you select the flip flop at 13:21 ? Will it be given in the question or do we have to choose it ?
I guess, it will be specified in the question. Here he has shown design procedure using T ff.
@@merida3975 Thanks !
You can choose any flipflop if it is not specified in the question.
He seems to have skipped step 6 at 9:25 where it says to decide the type of FF to be used
his teaching was so good. I could understand very clearly from his videos. Thanks a lot!
You are explaining clearly
Like these in college also didn't teach sir
point 6 is missing great job sir keep it up i will join you soon as i am currently busy in study i will be a part of you free and provide the lectures as much as i can
And it is very important
hello @nesoacademy ,im very thankful to you for your efforts and would like you to know that a lot of people are pirating your videos and uploading them onyoutube.plz report them
give the links of them to neso its wrong
Neso Academy Sir, thank you so much for your videos.
I have a doubt. Are synchronous sequential circuits the same as clocked sequential circuits?
@@neethajyothish7515 yes they are same , but i think you have completed this course now :)
@@indepthv7780 Haha yes :P
And i am done for tomorrow's presentation..thankyou so much
Man you are Awesome! I am referring your lectures only for my exam :D
Hi man! what are you doing now! i mean what you do for a living now!
@@Astra20284 I wanna know too
@@Astra20284 i wanna know too
Thank you very much sir. U cleared every thing about this topics😢😢. Love u sir 😊❤
Sir , can you explain how you decided to take T as a flipflop??
Bhai tu bohot sahi padata h...
Congratulations on 1 million subscribers😀😀😀😀😍😍😍
Thanks. You are THE ONE.
step number 6????
it is T flip flop
@@elmir.ahadov but why?
@@ImAkaii it can be anything like d or t, depending on the question
HOW TO DECIDE WHICH FLIP FLOP
@@wish_one_knot5006 I'd say JK if the two inputs are independent, D if the two inputs are always equal or you have only 1 input, T if you need Q to be complemented for each clock cycle.
Thanks for these amazing lectures! I have just one question - Can't we evaluate equations for next state and then implement them through Flip Flops. Like can't we write QA+ in terms of QA, QB and x, solve them through k-map, do the same for QB+ and then implement the circuit?
Yeah !! Did you get an answer for that? I know its 5 yrs back... still?
@@nannubedi7773 Yes, you are correct. In digital circuit design, it is common to first write the Boolean equations for the next state of a flip-flop or sequential circuit and then implement the circuit using logic gates and flip-flops.
One approach to implementing a sequential circuit is to write the Boolean equations for the next state of each flip-flop in terms of the current state of the flip-flops and the input signals. These equations can then be simplified using Boolean algebra or Karnaugh maps to obtain a minimized form. The minimized equations can be implemented using logic gates and flip-flops.
For example, suppose we have a sequential circuit with two flip-flops, QA and QB, and an input signal x. We want to design a circuit that computes the next state of the flip-flops, QA+ and QB+, based on the current state and input signal.
We can write the Boolean equations for the next state as:
QA+ = f(QA, QB, x)
QB+ = g(QA, QB, x)
where f and g are Boolean functions.
We can then simplify these equations using Karnaugh maps or Boolean algebra to obtain a minimized form. The minimized equations can be implemented using logic gates and flip-flops.
So, to answer your question, yes, you can evaluate the equations for the next state and then implement them using flip-flops and logic gates. This approach is commonly used in digital circuit design.
@@ritwikdurga3855 goofy ahh chatgpt response
Sir, if possible please provide lectures on Memories and Logic Families
Please sir include asynchronous sequential circuit analysis and design as soon as possible .thankyou for your lectures
Thank you very very much !!!! u have saved us !!!! thanks for this amazing tutorial... Me and my friends are greatly thankful to u !!!
I am the 200th uplike.. Thank you for this wonderful teaching.
superb teaching style
Thank you, this video made it a lot easier for me to understand.
Wonderful explanation 👏
Sir how to decide the type of flip flop to be used. You didn't explained this step
For step 6 we can use any flip flop. I prefer using d flip flop as it's simple.
@@aqua6150 sir used T flipflop
@@madeinandhra_2610 did i tell he used d flip flop?
He doesn't know it.
You can use any flipflop honestly... As long as you know how that flipflop works and you know it's truth table, you can make it's excitation table and find the expressions... The rest is just simply implementing the circuit
@nesoacademy
Sir, at 6:33 you are explaining that state reduction is not possible for the state table that has been obtained. For P.S. {0,0} and for x=1 as input, N.S. is {0,1}. Also, for P.S. {0,1} and for x=1 as input, the N.S. is again {0,1}. So, the N.S. {0,1} is repeated. Moreover, for both of these rows the output y is the same and equal to zero (y=0 under the x=1 column). Hence, state reduction is possible as there is a valid repetition in the state table.
Sir can you please tell the procedure for performing the state reduction in the above mentioned case.
wonder y nobody else figured it out , i also have the same doubt
exactly i also saw it and they can be reduced
@@Aryan_agarwal830 but i found the answer to it . state reduction can only happen when the states have next state and output same for all values of input x s0 and s1 have same output and next state but only at s0 x=1 and s1 x=0 which is different input so no state reduction can be done
Sir How you directly use T FF? Plz explain... How we can decide that we need to use which filp flop inputs or its excitation table?
What a nice lecturer!!!
thanks for your so detailed and patient vedio, really appreciate
On what basis did you decide to use T flipflop?
its cheaper ig
thankyou so much sir. u put so much efforts to explain things to us
this came yesterday in exam😑teacher didnt teach it so .have to leave it so came here to see how this is actually done
Hello sir, first of all, thank you for your excellent lectures. But I've a question....
You've said on 13:56 that you are making the characteristic table for T-FF. But my ques is.. is this the characteristic table or the excitation table of T-FF?
Char table is taken
Its excitation table only..only the columns are interchanged
Can you explain again how you decided which flip flop to be used to implement
Very good explain sir✔thnx a lot
first of all, great lecture.
why did you use T flip-flop. can we use D flip flop instead?
@@nesoacademy Can you explain how you would decide what type of flip-flop to use?
Kindly make a vedio on "analysis and design of asynchronous sequential circuits", as soon as possible
Thanks!
But is there another video in which the state reduction method is actually demonstrated?
state reduction prerequisite for this video but it is covered later in the video. so you should move it before this video
Very helpful vedios tqsm ...
In circuit excitation table, what if we got flip flop inputs as don't care.. ?
That will happen when we use jk flip flop in step6.
these lectures are really god but one thing that i have to tell you that if any lecture is related to the another one then please mention that lecture number so we can easily go through that lecture and learn that i left.
These lectures are very helpful..Thank you so much neso academy..but I have a doubt..In my examination only input and outputs were given..so how to determine the state diagram from input and output..if anyone know that please comment here.. the input is=110101 and the output is=010100. so from this how to determine the state diagram??
how to decide that which type of flip flop is used for implementing the circuit ?
you are the best,salute :D
thank you so much sir for these wonderful lectures.sir please tell me in which lecture you have explaned circuit excitation table?
very well explanation
thanks for the video i didn't understand anything
You just left it half heartedly.
for implementation of citcuit is the input x will work like clock in both T flip flops
sir first of all a very thanking you for this video. My question is that if i have 5 states then in this case which flip flap can i use for implementation of circuit......please give the answer...!!
it cannot have five states. it can have states in the order of 2^n (i.e 2,4,8,16...)
Thank you brother
In this video step 6 tells to decide the type of flip-flop also. But u have not said anything about its type , whether it is JK , SR , etc.
please add some lectures on pulse mode and fundamental mode curcuit
Thnks you sir🤩🤩🎊🎊
can u please explain how to inplement the circuit?
yess it is important
Tomorrow is my exam- if you can please tell me how to implement last step, it will be a blessing.
sir can u tell me how to decide the type of flip flop to be used. this step is missing in the video. thank you!
Great lecture! Sir but my question says use jk flip flop. What changes I have to make to use jk flip flop?
thanks for the video it was very helpful
can you explain how to draw a logic diagram for this flip flop
c-i-r-c-u-i-t and then circuit :)) at 09:50
the video was great,but u have missed the step 6.I want to know the reason behind the use of T flip flop.
5:26
Can someone tell rhe the videonin which sir taught state reduction.
please make lecture on Analysis of Asynchronous sequential circuits. please sir....No good lectures available on youtube 😢😢
9:21
Can anyone please tell me how to find the type of Flipflop used?
Thank you fot the woderful explanation . Please also include design concepts with word descriptions for some prectical logical conditions
hello sir..Is it necessary to check for next state for both the inputs i.e., 0 & 1 or either of the state is same to reduce the
state ??
How do you know there will be 2 state variables in the first step??? I think you looked at the state transition diagram for that, but sometimes there is only verbal description of the problem, not diagram. How do we know the number of state variables?
Or is it directly related to number of states? If there is 4 state, then only 2 state variables. If there are 5 to 8 states, then 3 state variables. Is that so?
Yes.
This still does not make sense could you explain?
Thank you very much!
in state table, when ever you said that,to reduce state table there exists 1 0 state repeating please explain
its not redundant because in both the cases NS is different for x = 1 and the output is different too. two states are redundant only if the next state as well as output is completely same
@@ishitagambhir6610 I am only learning this right now, so I'm a little confused.
What about row 1 and 2, NS: 0 1 (x=1) output Y= 0 (x=1) ??
Thank you sir
your lectures are really good
but in this particular video you have missed step 6
Where did u explain the state reduction method?
sir , how you chose T f.f. for the designing of the circuit
Anyone from Kathmandu University watching before finals?
hi. If u can help me the first two steps.
A car has different light states on its head and taillight. For break,for normal light, for turning left, for
turning right, and the other is for hazard. Design a state machine that controls these state for
the car headlight and taillight.
A day to exams 🤲🏼🤲🏼🥰🥰
Sir these are these the same state machines which are used in theory of computation
Please explain step 9 and implement whole circuit
thanx a lot ....u saved me:)
great lecture!!
can you please tell how you just write Ta & Tb without using k-map??
There are many ways to simplify this.He simplified using boolean algebra.
please provide a video for the event driven circuits also.
Please send me the link of video where you have introduced "State Reduction Process" for the first time.
I have a doubt regarding step 3 why reduction is not possible because for present state 0,0 and 0,1 the next state same 0,1 and output same 0,0 (for x = 1)
I think lecture are too slow for the students who already know the concepts and only watching these videos for revision . Apart from this the whole series is very good and we can learn all the thing here from basics .
+Tejpal Rebari you can watch in two times speed ...
Thanks man semester already expired
Sir how do we get to know that T flip flops are being used ?????
we need more example about digital systems like keypad scanner
Can we draw the circuit excitation table directly...if there are no possible state reductions?