U4 L3.1 |Design procedure for clocked sequential circuits | Design clocked sequential circuit

[@raovlog7237]

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[@TechnoTutorials2783]

Thanku so much for feedback 😊😊
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[@Gracetub6981]

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[@TechnoTutorials2783]

Thanks

[@janhvinarayan1633]

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[@TechnoTutorials2783]

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[@shibanandasahoo956]

Lucid explanation.. Thank you mam.

[@TechnoTutorials2783]

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[@laxmansaud6887]

From nepal u r excellent mam

[@TechnoTutorials2783]

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[@a3rdtierguy864]

Mam if at 10:55 if i take x on y axis and (Qa)(Qb) on axis kya ye galat ho jayega please reply is there any rule for kisko x axis pe rakhna hai and kiso y pe please reply mam

[@carnage-g4t]

Thank you so much ma'am 🙂

[@Jasmin-ku9bq]

Thank you ma'am 😊

[@afewerkyalew2064]

beast le....

[@kavyasrirajadurai1368]

In design the input for KB will be through xor right

[@beh683]

thanks a lot mam

[@TechnoTutorials2783]

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[@arulsuperchannel9038]

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[@nimmybansal7808]

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[@Masakkalii]

Kuch nahi amjha

[@TechnoTutorials2783]

Tell me ur doubt ornu can check other question

[@Masakkalii]

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[@Masakkalii]

@@TechnoTutorials2783 state table me next state hi output rehte hay na fir output alag kayse next state se