I was using this with an Ultra96. When I started with an Interconnect and a BRAM generator/controller and then the DMA, it didnt work properly. Your approach (order) helped me skip what I think is a lot of tuning on the AXI interconnect. Thanks for this! I am very new to the program
Excellent tutorial! I'm using the 2021.2 versions of Vivado and Vitis but almost everything you described was still relevant and the scatter-gather DMA polled and interrupt examples both worked on the first try. Huge thanks for helping out those of us trying to learn this stuff.
Thumbs up! Subscribed! Thank you for making this. One suggestion is to minimize the TCL Console and Flow Navigator so that the Block Design is larger and easier to see without scrolling.
Hi, thank you very much for this great tutorial. Can we use these example codes in petalinux application or are there any petalinux DMA drivers for this purpose?
Hi, excellent tutorial. Thank you very much. I enter to download the sources but i can't find the xaxidma_example_simple_itrc, only the polling example, can you upload it to git?
This example have a for loop to generate incremental data and store in tx buffer(ddr4) and then initiate dma to transfer data from tx buffer to rx buffer(ddr4). Basically transferring data between ddr4 only. There is no example describing data transfer from pl rom or pl fifo to ddr4.
I just noticed that all your videos are from last couple of months. I am sure have seen your videos from few years ago. What happened, did your old channel got hacked or something?
Hello, your tutorial is good but it doesn't work for me, I did exactly the same, my bitstream generation was a success but with 132 warnings..I'm using the 2020.2 version and in SDK when I tried to run the application I'd an error, the tool said it cannot find the the ARM device and even in VIVADO when I tried to program the device I had this error [Labtools 27-3165] End of startup status: LOW all I know, it's that it's about voltage and the DONE pin register that does not have the good value...it's low instead to be high... I've already searched in the Xilinx forums but no real answer to this problem.. :(
I was using this with an Ultra96. When I started with an Interconnect and a BRAM generator/controller and then the DMA, it didnt work properly. Your approach (order) helped me skip what I think is a lot of tuning on the AXI interconnect. Thanks for this! I am very new to the program
Excellent tutorial! I'm using the 2021.2 versions of Vivado and Vitis but almost everything you described was still relevant and the scatter-gather DMA polled and interrupt examples both worked on the first try. Huge thanks for helping out those of us trying to learn this stuff.
Thumbs up! Subscribed! Thank you for making this. One suggestion is to minimize the TCL Console and Flow Navigator so that the Block Design is larger and easier to see without scrolling.
In this example using the driver seems much more difficult code to read. Why not stick to access with pointers as you did at the beginning?
if i want to send my own data? which axi interface should i connect my own RTL port to in the block design?
Hi, thank you very much for this great tutorial. Can we use these example codes in petalinux application or are there any petalinux DMA drivers for this purpose?
No, these are standalone applications. There are AXI DMA drivers for PetaLinux, but we don't cover them in this tutorial.
keep up with your excellent tutorials!!
If I want to debug my ip in block diagram, how can I simulate this block diagram to view waveform?
Hi,
Iam using two axi dma channels separately connected to the two pl ddr4,i want to start both axidma at a time,how to do?any suggestion...?
Hi, excellent tutorial. Thank you very much. I enter to download the sources but i can't find the xaxidma_example_simple_itrc, only the polling example, can you upload it to git?
Hello, what data is actually being sent and read in this example?
Can this data be user defined as well ? If yes how do we go about it
This example have a for loop to generate incremental data and store in tx buffer(ddr4) and then initiate dma to transfer data from tx buffer to rx buffer(ddr4). Basically transferring data between ddr4 only. There is no example describing data transfer from pl rom or pl fifo to ddr4.
I just noticed that all your videos are from last couple of months. I am sure have seen your videos from few years ago. What happened, did your old channel got hacked or something?
I deleted my account by accident. Sounds crazy I know..
@@fpgadeveloper Yes it does :)
Hello, your tutorial is good but it doesn't work for me, I did exactly the same, my bitstream generation was a success but with 132 warnings..I'm using the 2020.2 version and in SDK when I tried to run the application I'd an error, the tool said it cannot find the the ARM device and even in VIVADO when I tried to program the device I had this error [Labtools 27-3165] End of startup status: LOW all I know, it's that it's about voltage and the DONE pin register that does not have the good value...it's low instead to be high... I've already searched in the Xilinx forums but no real answer to this problem.. :(
And I have a zedboard zynq-7000
@@igorzeh7182 i get that error when I do not have board configured to JTAG mode
Excellent
Thanks a lot ❤
Thanks!
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