Відео

I’ve been messing with Vivaldo for a year now and this is the first example I’ve run through that has worked as advertised. A bit baffled as to why this is the case. Using Digilent EclypseZ7 board, hopefully getting ADC data into the axi stream successfully at some point. Always a struggle except for this time.

Whats the output of this FIR filter I have to connect it to multiplier . So to make RMS calculation of it,

This tutorial no longer seems to work in 2024. Does anyone know why?

Greater video. Thank you

I know this is a bit older, but I think it should be stated that this is not truely HDMI. This uses the base pynq video library which actually runs dvi over the hdmi interfaces

Thumbs up! Subscribed! Thank you for making this. One suggestion is to minimize the TCL Console and Flow Navigator so that the Block Design is larger and easier to see without scrolling.

Why did vivado add the AXI interconnect? Is that because adder.cpp pragma is set to use INTERFACE s_axilite?

The board files location moved to personal directory in 2024... <main drive, mostly C:>/Users/<your_id>/AppData/Roaming/Xilinx/Vivado/2024.1.1/xhub/board_store/xilinx_board_store

If I want to debug my ip in block diagram, how can I simulate this block diagram to view waveform?

Interesting video. Is the video you are using for showcase in Sarajevo? I recognize the street view.

Make the algorithm in HLS/C then add to Vivado as IP Design, finish the block then export/generate BitStream to be called in Overlay.

Basically, using FPGA accelerator require 2 steps : - Design / Compile a IP Design into bitrsteam - Having data sending to such device to await result back

Hi, Great video. Which functions did you use for the computer vision. Did you use OpenCV? I am wondering if you use openCV on the PYNQ if it also accelerates the OpenCV functions. I need to detect faces with openCV but i need a faster solution then running a python script on a PC. So thats why i am looking into PYNQ.

Is this a better board than zturn ?

Don't ya change Jumper ?

25:25 - Plug MicroCard > Z-Turn 25:36 - Power Up with mini-USB 26:10 - Plug Ethernet Cable

Is it possible to implement YOLO with ZCU106 board?

In this example using the driver seems much more difficult code to read. Why not stick to access with pointers as you did at the beginning?

Hello, I follow your videos closely. I subscribe to your channel. I watched with admiration how you increased the FPS. Can you do the same for object recognition on the pynq z1 board? This is my undergraduate graduation project. I'm wondering how you upgraded the system via vivado. Can you please make a video about this? It will be watched a lot.

Is it the same if I use this as it is in vitis?

Very helpful and intuitive explanation, thanks a lot

hello , can i have you email adress please

Hi, thank you very much for this great tutorial. Can we use these example codes in petalinux application or are there any petalinux DMA drivers for this purpose?

That is insane!

drive.google.com/file/d/1-HID_agx68lPmJRrtrdaprMWZ-S0_RSr/view?usp=drivesdk

thank you.

Maybe not the smartest question, but: Is the hello world script being run on the PL (Programmabla Logic) or on the PS?

Thank you for your explanation and let me know a lot about axi stream. It would be better if you could explain the code you changed

Sorry for forgetting to add the code link to the video. You'll find the code in the blog post: www.fpgadeveloper.com/2017/11/creating-a-custom-axi-streaming-ip-in-vivado.html/

Can you share code of your video *Creating a custom AXI-Streaming IP in Vivado* pleaseeeeeeeeeeeeeeeeee

Can you share code of your video *Creating a custom AXI-Streaming IP in Vivado* pleaseeeeeeeeeeeeeeeeee

Can you share code of your video **Creating a custom AXI-Streaming IP in Vivado** pleaseeeeeeeeeeeeeeeeee

Can you share the code please?

Super helpful, thank you very much

Why you did not generate the block design from scratch? Is that from a reference (another video etc.) or anywhere else?

Thanks!

Great video! I am having Z-turn-v2 board and planning to create a project with ethernet in PL using gmii-to-rgmii IP, hope it will work

if i want to send my own data? which axi interface should i connect my own RTL port to in the block design?

not useful

Excellent

This video is cheating and fake. It simply does not work under current version of Vivado/Vitis 2022.2.2.

Hello, what data is actually being sent and read in this example? Can this data be user defined as well ? If yes how do we go about it

Nice!

南方科技大学李昊龙实名观看！

Wow! Just started working on PYNQ, wanted to see how good hardware acceleration can be

awesome video sir..can you make any project video for arty a7 100t?

11:10 it seems you need the .hwh file as adder.hwh from the hw_handoff subfolder next to the bitstream file on your pynq, otherwise the pynq will show an error message that it cannot locate the bitstream

Hi, Iam using two axi dma channels separately connected to the two pl ddr4,i want to start both axidma at a time,how to do?any suggestion...?

Hi, excellent tutorial. Thank you very much. I enter to download the sources but i can't find the xaxidma_example_simple_itrc, only the polling example, can you upload it to git?

Excellent