AXI Memory Mapped Interfaces & Hardware Debugging in Vivado (Lesson 5)
Вставка
- Опубліковано 1 сер 2024
- The Xilinx ZYNQ Training Video-Book, will contain a series of Videos through which we will make the audience familiar with the architecture of the ZYNQ device. Then, we will teach how one can design embedded systems for the ZYNQ using the Vivado environment.
- Наука та технологія
![The AXI Protocol, AXI MM and AXI Streaming Interfaces [English]](http://i.ytimg.com/vi/Ko3wmIVsOtM/mqdefault.jpg)
These videos are a life saver! If only Xilinx made videos that were half as helpful...
Dr.Sadri,
Thank you for this excellent series of lectures. Nicely done!
I look forward to watching all of them.
AN UPDATE THAT WILL HOPEFULLY HELP OTHERS. As everyone has said, thanks for this, it's invaluable, I've been able to recreate something very similar with Vivado 2019.2 The XMD shell used above has been dropped but they provide the new "Xilinx Software Command Line Tool" XSCT whicg appears to do the same thing. There are multiple cores now so the commands have changed a bit..........
Open the XSCT shell
Navigate to your working directory (tcl shell, directory separators are / not the windows \)
Type "connect" , this should connect the shell to the JTAG server (I think)
In order to decide what target you want to select type "targets". (We're talking to the PSU so note that number down (5 in my system), you can skip this when you know the number)
Type "targets 5" (or the number you selected above)
Type the following.....
"source init_psu.tcl"
"psu_init"
"psu_post_config"
"psu_ps_pl_reset_config"
"psu_ps_pl_isolation_removal"
The clocks to the PL should now be configured, the reset removed and the FPGA logic can be programmed and interacted with like normal (I think this can probably all be done with a single tcl script).
[Update] I think you have to change the target to one of the ARM cores to do a memory read or write operation. [/Update]
2023, I'm getting a bug where the last write address doesn't work the first time in cases. Also use -force to force a write/read across GP0
Even in 2022, and with ZYNQ-Ultrascale+, these videos are useful. Xilinx (now AMD) should learn from this.
Fantastic Sir. I commend you on your educational style. Both fundamental and extensive but humorous.
Very educational and informative. Well done. Keep up the good work. It is very much appreciated.
Thank you Dr. MohammadSadegh for a most excellent tutorial. Well done!
Valuable and informative session and i got good overview of using AXI. Thanks a lottttt. Expecting more lectures from you
My Good man, after sever or so year...I am studying the same situation and I really really appreciate for sharing this video. Thank you brother.
It is so much easier to follow your instructions videos, compared to searching in Xilinx' s pdf's for the information I need.
I have 3 monitors connected to my desktop. The middle with your video in Full HD. My Vivado on the right screen and my SDK on the left. Then, just pause the video and replicate what you are doing :)
thank you so much. your lecture helped me in viewing axi4 read/write transactions through ILA. previously i failed to get it by VIP.
As for today, this is still a very informative and useful video. I was able to reproduce it on zcu102 with 2018.3 version of the tools. There are some differences here and there, but the principles are the same. Thank you very much for the high quality contents!
still here in 2023 using a Pynq-Z2 with Vivado 2022.1 😄
Really helpful. Keep up the good work. Greetings from Technical University Of Crete Greece!!!
Thank you very much for the effort and for the contribution you are making!
Thanks for the excellent video! It is really helpful for me.
Thank you for this fantastic video lesson!! Learnt so much!!
Excellent presentation!!!
Awesome video, really useful !
Excellent video, thanks!
this video is pure gold. Dr. Sadr, thank you. We love you 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFF.
Thank you so much for your great Video , its very helpful and well explained
Thank for the excellent tutorials
It is the best video i have ever seen , thank you so much !
Great video, it looks like Weather Forecast
Excellent video
Thanks for the video.
Really good. Thanks Mr. Sadri
Dr.Sadri :P
This is a wonderful lecture
Thank you very much :) The next Lecture will be online soon.
Thank you so so much !!!
Thank you, excellent!
Not all heroes wear capes.
Hi Sadri,
I have a question on the zynq AXI GP port. At what clock frequency will I be getting data out of the zynq , is it the FCLK0 and when we send the data back to the Zynq it is the same clock frequency ?
Dr. Sadri I tried to use CDMA for transferring large data from DDR to block ram but if I store my data on different locatoin other than 0x00000000 the data transferred to Block ram is not the same(corrupted) is there any other location (other than 0x00000000) where I can store my data(its large around 64 k deep and 32 bit wide) on DDR ?
Hi Dr Sadri
I have a question. How can i debug a signal many times with ILA? I am using vivado logic analyzer to debug the output from my hls design. How can i configure the analyzer to capture the data when multiple interrupts occur?
Thanks
Thank you sir
What did your trigger script do to cause the DMA to perform the transfer? PG034 says "Write the number of bytes to transfer to the CDMA Bytes to Transfer (BTT) register ... Writing to the BTT register also starts the transfer."
thank you.
hope the useless technical training people @Xilinx watch and learn how to explain their system
They just want people to attend their courses for money.
Perfekt .
Hi Dr. MohammadSadegh.
I have question, at 55:01, I see 1st and 2nd adress line is base on M_AXI_GP0 address because it connect to M_AXI_GP0 of PS.
But how do I can check if 3rd adress line is correct or not? which address it base on? I check in TRM that C000_0000 is reserved address. Why we assign it to reserved address?
Thank you.
How can we repeat this exercise for Microblaze based system in Vertex 7 FPGA?
Studing AMBA specification is an overkill, because not all features are supported by Xilinx. For example the mentioned memory regions aren't supported at all.
The primary reading for the topic should be Xilinx UG1037
Is the Block Memory on the PL side or the PS side?
Hi.....Myself Brijendra Sharma @IIT Kanpur,
My questions are ........I want to boot the Zynq Ultrascale +MPSoC(XCZU9EG-2FFVB1156E) & RFSoC(XCZU28DR-FFVD1156) devices. So i need your help that how we can simulate such booting application on vivado Hlx edition software.
Is there any simulation vedio??
Also in vivado when we create the new project, There is option of ports/ boards. Can we board for simulation for testing Booting. If yes than how we can do this job??
Please help me.
Brijendra Sharma
P Scientist @IIT Kanpur
Is there a tutorial that has just an extremely simple example like sending a variable floating point number from one block to another? Nothing fancy or even useful, just a simple exchange of data from one block to another.