STA lec9 setup time concepts - part 2 | static timing analysis tutorial | VLSI

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  • Опубліковано 22 гру 2024

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  • @Narennmallya
    @Narennmallya 2 роки тому +2

    Thanks!

  • @the_harshavardhan
    @the_harshavardhan Рік тому +2

    Why is that the skew is subtracted from the clock-period. Shouldn't it be added to the clock-period. This is extra time that the data gets to arrive at the capture flop. Unless we are assuming that the clock arrive at the capture flop before the launch flop. Which I am sure is not the case considered here.

    • @VLSIAcademyhub
      @VLSIAcademyhub  Рік тому +1

      Skew is subtracted when skew is negative and is added when it's positive
      Regards
      VLSI Academy

  • @chamis8002
    @chamis8002 2 роки тому +3

    @9.48, You take Tskew and Tuncertainty Separately When calculating TR. Here, Tuc should be corrected as Tjitter, right? In an earlier lecture, you said Tuncertainty = T skew + Tjitter..

    • @ragulnivash7525
      @ragulnivash7525 4 місяці тому

      Have same doubt! Need a clarification on this.

  • @subhranilpatra8813
    @subhranilpatra8813 2 роки тому +5

    Sir in required time calculation as u r taking positive skew... skew should be added i think.

  • @DalasYoo
    @DalasYoo 3 роки тому

    Well one question I have on the setup time is how the setup time violation of the clock gating cell Enable signals. In that case sometimes the timing report doesn't show the clock required time. Would this be normal?

  • @vijay4a4
    @vijay4a4 2 роки тому +2

    Hi sir,
    Is skew is add or subtract to Required time?
    Please clarify me because I saw in some sites, skew is added to required time

    • @Games-uz2rd
      @Games-uz2rd 5 місяців тому

      It is actually added as clock skew makes the capture flop to trigger late and so the data required time will increase

  • @luckeylokesh1952
    @luckeylokesh1952 2 роки тому

    Tcq how to consider sir

  • @paraprannoy3732
    @paraprannoy3732 2 роки тому

    If we are given some value for Jitter...it can come before or after the clock edge we can't predict it. But for setup, we need to consider the worst case so we should subtract the Jitter from RAT.
    Whereas when some positive value is given for skew...it helps setup by moving the capture clock edge to the right...so we need to add it to the RAT. There is nothing like uncertainty like Jitter in this case. So my doubt is in this example you should add skew to RAT but u didn't. can you please clarify this?
    I know skew and Jitter are included in uncertainties...and uncertainties should be subtracted from RAT but positive skew helps setup right? so we must add it to RAT right? @VLSI Academy

    • @paraprannoy3732
      @paraprannoy3732 2 роки тому

      @@VLSIAcademyhub I heard that in the pre-CTS stage only we consider skew, post-CTS we get the exact delay so there will be no skew in uncertainty, only Jitter involves. So I assume that skew=1ns which u said in the video is pre-CTS and though it is a positive value, we need to subtract it from RAT for the worst case always?
      So they'll give one skew value which we need to subtract always for setup for the worst case? they'll never give a negative setup value, right? Sorry, I was a bit confused, thanks for the fast reply.

  • @rnsuriyakiran5065
    @rnsuriyakiran5065 2 роки тому

    some correction about equation while dealing with latched data and problem equation
    about uncertainty involving without involving

  • @rohan2630
    @rohan2630 2 роки тому

    If time for T2 is more than it should be added in total time for setup time violation

  • @ranveerdhawan744
    @ranveerdhawan744 2 роки тому

    If skew is positive it must be added in Tclk .