STA lec14 defining reg2reg constraints | static timing analysis tutorial | VLSI

[@shri1527]

So do we need to write the TCL contraint command to set max combinational delay ...what is the command?

[@MohanKumar-m1h]

Is zero skew is possible?

[@VLSIAcademyhub]

In theory yes and in reality NO
And it's not favourable for design to have zero skew