Concepts have been explained extremely well and with proper depth. The best one so far to clear all your doubts. The detailed explanation and problem solving using timing diagram is the best way to make someone understood STA to its depth. Efforts are highly appreciable and commendable.
I have watched the complete video lecture thank you Himanshu sir for explaining all the timing diagrams and concepts behind it. I have also referred my friends to watch this. pls come up with constraints, crosstalks, CDC, and timing, area, power reports concepts
Thanks a lot bhai, loved the whole video. I've previously encountered these topics in two of my NPTEL courses where i was able to solve problems but not with this depth and intuition, i used to mess up alot and get confused. This video made my concepts more stronger.
very great explanation sir!! Appreciate your efforts with the timing diagrams. It may have taken you a lot of time to draw them individually. Thank you very much for the video
this is a masterpiece that you have created sir i love the way you teach coders have striver and love babbar now we can proudly say we have himannshu agarwal for core
trust me the best sta video i have found till now. I mean few months back I searched a lot for videos for sta but this is far better and at par as compared to others. Atleast this video came before my placements . Thank you!!
such a beautiful explanation of all the concepts, the way you explained all the difficult concepts with such ease and that too leaving us with no doubts at all.. really really commendable. Thankyou so much for the video! It is perfect🎉
Thank you very much Himanshu bhaiya for this awesome video. After watching this video I understood STA in a easy manner, as a result I was able to do all the sta related questions correctly yesterday :) Thank you again. Want more videos on VLSI physical design flow :)
Superb video sir , till now i thought i was good in these set up and hold time analysis .. but after watching this video , i would say its worth my time because i learnt new appraoches and cleared my misconceptions in this concept ..good job sir , keep going 🔥🔥🔥
Himanshu , your concept knowledge and teaching is really good. Along with this it would be great for students if you can recommend good books and literature which they can refer.
there should be a scan QR code here like we take in marriage lifaafa , so that directly can pay, haha, unbelievable feelings after all concepts cleared, feeling like big burden released, definitely who dont got in touch with you till now or your any sources, they are unlucky enough while preparing for gate and interviews
Timing diagrams ❤ thank you so much. im doing mtech at iiit allahabad,sir i wanna revise sequential circuits, can i get subscription for only sequential circuits playlist rather than total digital electronics playlist
Hello Himangshu!! Thanks for the video. I have a small doubt. The interviewer asked me the following questions. Can you please explain it once? - why setup and hold time is required? (Necessity) - what happens if setup and hold time are not met?
Setup time will ensure that data is stable before the clock edge arrival, so that the ckt can "prepare" itself to latch the given data. And hold time ensures that data remains stable for long enough time after the clock edge so that the flop can finish the process of storing the data efficiently. If setup and hold margins are not met, the ckt will fall into metastable state and your output will be unpredictable.
@@HimanshuAgarwal_ Yes, the definition of setup and hold time is clear to me. I want to know from where a specific time came. And if data changes after the clk pulse or before the clk pulse, it will give wrong data. How will it go into the metastable state? Thanks for your reply.
bhai hindi me padhya kro
English ahi bol patte toh
@@SAURABHKUMARJOSHI-f6y Which Organisation is hiring you to make such comments?
You just made your account 2 minutes back, I can see it.
Sir ignore this type of people .
Concepts have been explained extremely well and with proper depth. The best one so far to clear all your doubts. The detailed explanation and problem solving using timing diagram is the best way to make someone understood STA to its depth. Efforts are highly appreciable and commendable.
I have watched the complete video lecture thank you Himanshu sir for explaining all the timing diagrams and concepts behind it. I have also referred my friends to watch this. pls come up with constraints, crosstalks, CDC, and timing, area, power reports concepts
Thanks a lot bhai, loved the whole video. I've previously encountered these topics in two of my NPTEL courses where i was able to solve problems but not with this depth and intuition, i used to mess up alot and get confused. This video made my concepts more stronger.
Completed the video within one day only!!!Best video till date on yt of sta!! Nvr found all the pattern of questions in one place!!🔥
Great explaination man.Specially the timing diagrams ,completely understood the logic behind it.
very great explanation sir!! Appreciate your efforts with the timing diagrams. It may have taken you a lot of time to draw them individually.
Thank you very much for the video
this is a masterpiece that you have created sir i love the way you teach coders have striver and love babbar now we can proudly say we have himannshu agarwal for core
a lot of depth in concept ..thank you so much . need FYQ for emt if possible
Your lecture helped a lot sir. Thanks a lot for making this available publicly.
trust me the best sta video i have found till now. I mean few months back I searched a lot for videos for sta but this is far better and at par as compared to others. Atleast this video came before my placements . Thank you!!
45:26 , the hold time must be >= rather than
such a beautiful explanation of all the concepts, the way you explained all the difficult concepts with such ease and that too leaving us with no doubts at all.. really really commendable. Thankyou so much for the video! It is perfect🎉
Thank you very much Himanshu bhaiya for this awesome video. After watching this video I understood STA in a easy manner, as a result I was able to do all the sta related questions correctly yesterday :)
Thank you again. Want more videos on VLSI physical design flow :)
Superb video sir , till now i thought i was good in these set up and hold time analysis .. but after watching this video , i would say its worth my time because i learnt new appraoches and cleared my misconceptions in this concept ..good job sir , keep going 🔥🔥🔥
loved these contents bhaiya ......want more vlsi oriented vedios please
best video ever on STA. Thankyou sir!
thank you so much, all the doubts I had on STA were cleared after watching this video.😄
Great explaination
Again phenomenal video sir as always 😊
Very useful and interesting video. Thanks for uploading. 🙏
Thank you himanshu sir ❤❤❤❤❤❤❤❤❤❤❤❤❤❤❤❤❤️❤️❤️❤️❤️❤️🔥🔥🔥🥺🥺
Great session sir😀
Excellent content
Thanku so mucch sir for this tutorial...ur lectures are always so beneficial ❤
Bohot helpful he ye video bhaiya
Thanks from BE College 😀
Amazing Video Sir 🔥🔥
Himanshu sir you must write your own book of digital and analog ❤❤
Great Explanation sir
Thankyou sir! ❤Very fill full explanation
If I further any doubt in DSD I would like to prefer your video Only🙏
Hi, professor. Thanks for this lecture 😊
Thank you himanshu sir ❤🎉
Awesome explanation sir❤
Best on Internet 🔥
evela madkondu kelsa engee madtya guruu, super bro neevu
nicely explained sir
Thank you sir it gonna help a lot
Thank you sir.
The saviour ❤
Awesome ❤❤❤
Good content explained
perfect perfect perfect
luv u bhai
Best explanation
Hats Off to you
Himanshu , your concept knowledge and teaching is really good. Along with this it would be great for students if you can recommend good books and literature which they can refer.
Yeah, Books I have recommended in some short on my other UA-cam channel "PrepFusion"
at 1:25:18 isn't the output invalid as it is SR flip flop with S=1 and R=1??
there should be a scan QR code here like we take in marriage lifaafa , so that directly can pay, haha, unbelievable feelings after all concepts cleared, feeling like big burden released, definitely who dont got in touch with you till now or your any sources, they are unlucky enough while preparing for gate and interviews
Timing diagrams ❤ thank you so much. im doing mtech at iiit allahabad,sir i wanna revise sequential circuits, can i get subscription for only sequential circuits playlist rather than total digital electronics playlist
@@hemanththangi6957 sorry, that wouldn't be possible
Okay 😊.I have seen a lot videos on timing analysis but your explanation have unique style keep going sir 🙂
please cover effect of jitter and derate in STA
best video
tq sirrrrrrrrr
Nice sir ...
❤❤❤
Hey himanshu Do I have to follow the whole lecture for gate ??
🤩🤩
Sir, is the th2 = hold time of FF2?
2:35:30
Sir! While giving the formula's you written Th2 >= ...... but, initially you said it is
@@nikhilakkireddi250 typing error. Modified later on
@HimanshuAgarwal_ Ok sir! Thank you
Sir, how long will this be public?
Always.
@@HimanshuAgarwal_Ok sir❤❤❤❤❤
This Video is like Ford vs Ferrari movie
Hello Himangshu!!
Thanks for the video.
I have a small doubt.
The interviewer asked me the following questions.
Can you please explain it once?
- why setup and hold time is required? (Necessity)
- what happens if setup and hold time are not met?
Setup time will ensure that data is stable before the clock edge arrival, so that the ckt can "prepare" itself to latch the given data.
And hold time ensures that data remains stable for long enough time after the clock edge so that the flop can finish the process of storing the data efficiently.
If setup and hold margins are not met, the ckt will fall into metastable state and your output will be unpredictable.
@@HimanshuAgarwal_ Yes, the definition of setup and hold time is clear to me.
I want to know from where a specific time came.
And if data changes after the clk pulse or before the clk pulse, it will give wrong data. How will it go into the metastable state?
Thanks for your reply.
According to me answer is parasitic capacitance, it needs tsu amount of time to charge or discharge according to change in logic.
Sir please provide notes
@@kadajaganmohanachari join the telegram group. Will be provided there
Please don't repeat the same topic again and again actually this lecture will not require 3hours it will be completed within 2 hours