DDS Compiler(Direct Digital Synthesizer)/Analog Signal Generation of Zynq Processor in VIVADO.

#dds #zynq #fpga #vivado #vhdl #verilog

[@RenegadeFury]

Thanks for this, this was really straight forward. Finally understand how to use the DDS. Most online explanations got too carried away with math. I just wanted to generate 1 mhz fixed sine wave with a 100mhz system clock and this works great for that

[@AdvanceZYNQseriesFPGAprojects]

@Barack Lasagna..thanks for ur valuable comment…Please be with my channel/subscribe for more updated tutorials..
Also share my channel to dear ones..

[@tobiasyang3572]

Very practical tutorial!
One question, I tried to scale up to 4 channel sine wave generation, so I kind of multiplied this structure 4 times. However, I can not get received signal from ADC. Have you tried to generate more than 1 channel? Thanks.

[@mohdbilal4182]

Nice effort. Please keep it up. 👍

[@AdvanceZYNQseriesFPGAprojects]

Do subscribe my channel..thanks!

[@yarenkaya7872]

Is there anyone who is interested in generating sinusoidal without using Zynq and in VHDL not Verilog?

[@lalithashutosh3356]

Hi sir, great content it helped me a lot. Is there way to reach out to you, as have some doubts in procedure and it be greartly indebted to you for your help.

[@nunustone7133]

Hi,
thx for the video.
It's also possible to generate a square signal for a trigger generator with the DDS element?

[@AdvanceZYNQseriesFPGAprojects]

This DDS only generates sin/cosine signal..then u will have to add circuit to shape that signal to become square signal..

[@nunustone7133]

@@AdvanceZYNQseriesFPGAprojects thx:)

[@himabindu292]

Thanks a lot

[@sachinwaghmare6122]

Thank You😍😍

[@nikolaykostishen6402]

Thanks man!

[@AdvanceZYNQseriesFPGAprojects]

Don’t forget to subscribe for future update..!

[@ZaidEngComp]

Perfect

[@millenialish2278]

What would be phase angle increment values for a 1khz sine wave?

[@krishnavivek1052]

Nice 👍

[@geenabenga9741]

Hi. Is a bitstream generation possible after those steps? Can I make my fpga generate this sinus wave now? Thank you very much!!

[@AdvanceZYNQseriesFPGAprojects]

Yes..u can generate bit file

[@geenabenga9741]

Thank you!! I tried but what I need is an output from the output Port of a Red pitaya. Do I need a DAC in the block design?

[@SujitDas-xf1bc]

Thanks for sharing..

[@vaishnavikapilavai4066]

Please upload a video which shows the procedure to generate analog waveforms(sine waves, step waves), etc, in vivado 2018.3 version, chipscope. FPGA Board is Nexys Artix 7 100t, csg 324. Please upload it immediately.

[@utube4anbu]

how to control amplitude of sine wave?

[@tejaswininivarthichandrash597]

Hi
Add wave command gives me the error that nothing was found for clk and probe. How do i resolve this?

[@AdvanceZYNQseriesFPGAprojects]

U will have to right click on clock and tick force clock..

[@tejaswininivarthichandrash597]

@@AdvanceZYNQseriesFPGAprojects That also is giving me the same error later. I can't force clock or even add the cl and probe to the waveform

[@AdvanceZYNQseriesFPGAprojects]

@@tejaswininivarthichandrash597 can u share screenshot?

[@tejaswininivarthichandrash597]

@@AdvanceZYNQseriesFPGAprojects I'm not sure how to share screenshot in youtube comments but I will copy paste the errors.
The first error:
This I get when I right click on clk and probe of ILA and click on add wave. It doesn't get added to the simulation wave window and error comes
ERROR: [Wavedata 42-471] Note: Nothing was found for the following items: /\dds_compiler_wrapper:dds_compiler_wrapper:\/DDS_Compiler_i/ila_0/clk
ERROR: [Common 17-39] 'add_wave' failed due to earlier errors.
So instead of using add wave command I added the clk and probe by drag and drop and tried to do the force clock and I got the following error:
ERROR: [Simtcl 6-8] No such HDL object /\dds_compiler_wrapper:dds_compiler_wrapper:\/DDS_Compiler_i/ila_0/clk

[@tejaswininivarthichandrash597]

@@AdvanceZYNQseriesFPGAprojects Any suggestion?