I’ve simulated this model using Xilinx system generator exactly the way shown on this video. I’ve used 16 bit unsigned with 6 fractional bits and used the constant 209.71875. According to this video I supposed to get 61.44MHz sine signal, instead my simulation resulted a sine signal of 61.5234 MHz. Any suggestions as what went wrong with my simulation.
You will get the 61.5234 MHz frequency when you will set tunning word to 209.999872 - very close to 210. So maybe the generator rounds up your constant to the nearest integer?
Excellent overview of the DDS theory and implementation. Thanks very much!
Great overview of dds. I am wondering how adding the random noise helps to reduce the distortion of the dds output.
excellent overview thanku
Excellent
Thank You!!!!!
I’ve simulated this model using Xilinx system generator exactly the way shown on this video. I’ve used 16 bit unsigned with 6 fractional bits and used the constant 209.71875. According to this video I supposed to get 61.44MHz sine signal, instead my simulation resulted a sine signal of 61.5234 MHz.
Any suggestions as what went wrong with my simulation.
You will get the 61.5234 MHz frequency when you will set tunning word to 209.999872 - very close to 210. So maybe the generator rounds up your constant to the nearest integer?
What is meant by the Modulas (M) ?
Hi friend, could you send me this code please?
Hm, crypto