FPGA FM Modulator with DDS

This is video I'm describing how to use the DDS (Direct Digital Synthesis) as a frequency modulator by changing the phase increment. The video is presenting the principle of DDS and different tradeoffs A Vivado example can be downloaded as an example and the presentation used in video as well. Quality of video is not great I hope the information will compensate for that.
Enjoy!
design files can downloaded from my Blog page
www.adaptivede...

[@phillipneal8194]

Thank you very much for your video. It was very educational. Also, it was the first video I have seen where FPGAs are used to modulate (or demodulate) a signal.

[@adaptivedesign8795]

I'm glad you like it check the FM Stereo radio transmitter video - where I used AM modulation of the multiplex stereo and FM modulation for the carrier. I'm sure you'll find that interesting. ua-cam.com/video/MJxTVts67yg/v-deo.html
Have fun!

[@cybersecuritydeclassified4793]

Thank you for sharing your knowledge!

[@adaptivedesign8795]

My pleasure!

[@benish0r]

Very informative, I learned a lot. Thank you!

[@adaptivedesign8795]

Glad it was helpful!

[@FabriceWiotte]

hello
what is the type of data provided on the "audio" modulation input? it must be in hexadecimal
thank you for your answer
cordially

[@adaptivedesign8795]

Hi There,
The signal is PCM digital is signed binary., two complement format, for instance when you want FM modulation, you choose the phase increment value, which in turn will give you the center frequency (the carrier) and the audio samples will add/subtract from that value (depending on the sign of the samples) and will "deviate" the carrier. (will frequency modulate the carrier)
please let me know if I explain sufficient and clear. I have another video which my explain it better (not sure if watch it already) ua-cam.com/video/U8DqF9C_O2I/v-deo.html

[@FabriceWiotte]

Thank you very much for your answer.
I would just like to know how the VHDL code is built in the PHASE_INC module befor the DDS IP core of your video ua-cam.com/video/U8DqF9C_O2I/v-deo.html
Best regards

[@adaptivedesign8795]

@@FabriceWiotte Not much code in VHDL is just an signed adder (min 22.22 sec) that I inserted as a block in Vivado, one one input takes a constant value in hex (the carrier) and ont the other input it takes the audio stream. The output of this adder is conected to the DDS on the phase_inc input.

[@arpit4681]

Thanks ..for this informative video..

[@adaptivedesign8795]

Great! Thanks for watching.

[@fc3fc354]

Hey guys,
Sorry for the question it's only a little bit related to the video.
For implementing a Hamming Window on some signal (that will be inputted sequentially) should i just store the hamming coeff. In ROM and multiplu to the input or calculate coefficients dynamically with DDS giving us the coefficient value
Or We would use Dynamic calculation only when we do not know the value of the input size

[@adaptivedesign8795]

you have a few choices (nothing to do with the DDS) you can pre-compute your hamming scaling coef (or any other window function) store them in RAM and multiply them with your incoming samples as they come. I would do this a AXI stream IP core which can be configured for different lengths and different type of windowing. (or configurable on the fly if necessary)
Have fun!

[@fc3fc354]

@@adaptivedesign8795 thanks a lot
You are being a very good support to the FPGA community 😄

[@justotalkalottashit8392]

I have a custom ka-band direct digital synthesizer from NASA, that i bought at a surplus sale. Wondering what to do with it as it is missing one part, has these 3 brass colored modules inside of it labeled 75mhz and one is missing.

[@adaptivedesign8795]

I seriously don't know what to say...

[@Amirhossein_1996]

Hi Mr. How can i send modulated signal from fpga to receiver? Does DDS can send that?

[@manuelsanchez1262]

Hello. So would the adder be the equivalent of the "phase_inc" block you have in your other videos? I am trying to piece the whole radio together (i.e., the final block diagram of the radio) but this doesn't exactly go over the phase_inc block. Instead of audio like you do here, we would be passing in the 16bits from the dc_off_remove block to the adder right? Also, on the phase_inc block, you have two clocks, aclk and dds_clk, why is this?

[@bob_mosavo]

Thanks 👍

[@adaptivedesign8795]

Welcome 👍

[@samjef8131]

perfect. thanks a lot