Clock frequency divider using decade counter

[@arpittiwari7695]

I didn't get what does connecting certain output signal to RESET signal mean logically?
does that mean logical OR of output pins and RESET pins?

[@TechnicalBytes]

Dear Arpit, RESET signal goes to all the flip flops inside the design. we can choose reset value of any flip flop. When we apply RESET signal as HIGH, all the flip flops will go to the reset state irrespective of the inputs to the flip flops.

[@swetadash4887]

How to get 50% duty cycle here?

[@bharadwaj767]

Connect flip flops at the end
Negedge for half cycle, posedge for full cycle

[@arghya.7098]

we need external circuitry involving OR gates, posedge, negedge triggered D flipflop

[@anandkumar-bd2ru]

Thank u sir

[@TechnicalBytes]

Thanks !!