Answer 10% duty cycle. delay q1 by half of timer period by using Nededge FF . then Q1_modified and Q2 gives a output with 10% duty cycle. :) PS: Thanks sir , for helping me ,becoz of u, I am able to solve this type of qsts.
We can also create a 90% duty cycle and take the complemented output of that to get 10% duty cycle, but it will take a lot of hardware, it better to take (q1_ffn )and (Q2)
Hi, as per the explanation in this video, it is made convenient to design duty cycle of 10%, 20%, 30% ...90%. To get duty cycle of 33.3% for f/5, we have to think. If you know any trick to design, please share it with me. If you need it urgently, then we can think of its answer together.
Should do a neg edge trigger on Q1 and or it with the signals you tapped to avoid glitches in the clock you are generating as your OR gate switches from Q1 to Q2. assign new_clock = Q1 | delayQ1 | Q2 | delayQ2;
Your shift register is not initialized. There is no obvious way it was initialized of 5'b10000 before. It could be 5'b00000 or 5'b11111 after reset. The simulation of this will result in 5'bxxxxx.
![Clock divided by 3 || Explained step by step! [Frequency divide by 3 ] F/3 or F/odd number](http://i.ytimg.com/vi/wxUqxSE_F5A/mqdefault.jpg)
Fro 10% duty cycle, apply Q1 to the neg edge-triggered D-FF, apply AND gate for Q1, and the output of D-FF(neg edge).
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Get the 90% duty cycle after giving Q4 to neg edge... Then apply the same signal to inverter to get 10%duty cycle
Answer 10% duty cycle.
delay q1 by half of timer period by using Nededge FF .
then Q1_modified and Q2 gives a output with 10% duty cycle. :)
PS:
Thanks sir , for helping me ,becoz of u, I am able to solve this type of qsts.
Keep it up dear ..
Q1_ff (Q1 is input to negative edge flip flop ...Q1_ff is output)and with Q2 ..
ie F=Q1_ff.Q2 is with duty cycle 10%
This is one of the many options .. Q1 . Q1_ffn will also yield 10% duty cycle. But appreciate your understanding.
We can also create a 90% duty cycle and take the complemented output of that to get 10% duty cycle, but it will take a lot of hardware, it better to take (q1_ffn )and (Q2)
You are right.
@@TechnicalBytes Sir can we take two inverters acting as a buffer of t/4 delay each, in place of dual-edge ff. Will the ckt function same as above ?
Sahii hai medu..
use AND gate instead of OR gate, and inputs of AND gate are one flip flop output, and output of negative edge triggered flipflop
Can u explain briefly plz
same bro
Sorry for delayed response.. What will be the outcome by doing so??
Simply do FF1 or FF2 or (FF3 & clk) to get 50% duty cycle. No extra FFn is required.
pass q1 through -ve edge flipflop and take the AND operation with q2 you will get 10% duty cycle
After getting the output with 90% duty cycle, just invert it by passing through a not gate to get 10 % duty cycle signal.
Thank you sir. Keep guiding us..
Always welcome !!
Thank you very much very formative 👍👍👍🙏🙏
Glad it was helpful!
Negative edge to Q1.Q1_ffn it will give 10 % duty cycle because Q1 will remain high for only half period(negative level clock).
For 10% duty cycle, can't we just use AND gate for clock and Q1(or any other output)... minimal hardware..
no thts not f/5 then ,it will be f only
Invert Q1 , then delay it by half clock by using neg edge triggered ff, AND the desired result with Q1 to obtain 10% duty cycle
Hi, can we also achieve 33.3% duty cycle in this f/5 case. If yes , please let me know how?
Hi, as per the explanation in this video, it is made convenient to design duty cycle of 10%, 20%, 30% ...90%.
To get duty cycle of 33.3% for f/5, we have to think.
If you know any trick to design, please share it with me.
If you need it urgently, then we can think of its answer together.
@@TechnicalBytes for f/12 we can make 33.3% duty cycle
Too good explanation, thanks
Glad you liked it
Should do a neg edge trigger on Q1 and or it with the signals you tapped to avoid glitches in the clock you are generating as your OR gate switches from Q1 to Q2.
assign new_clock = Q1 | delayQ1 | Q2 | delayQ2;
The how can we generate negative clock for that extra flipflop?
Please explain how to divide the frequency by fractional numbers !! I am not able to access your other page
ua-cam.com/video/TgsyQgliuYc/v-deo.html
This is a member only video, plz press on the join button to get membership.
I'm thinking the output of this kind of "clock" may be glitchy. Also why would 50% duty be required if we just stick with using posedge clks?
Unless... you also run the output into a final flop.
Go through this video:
ua-cam.com/video/ng5RkwU0fHc/v-deo.html
Q1 AND Clock signal = 10% duty cycle
Is this correct?
one way is, to pass q1 output into a negedge flop which becomes q_ffn. invert this to get ~q_ffn. finally ANDing q1 with ~q_ffn.
Dear, what are you trying to achieve from this ? Can you please eleborate?
@@TechnicalBytes for 10 % duty cycle. (q1 & ~q1_ffn).
New ff with ip - Q1 and clock to negative edge and its output Q_FF
For Duty 10% = Q1 AND ~Q_FF
Right??
sir wht you mean with ffn.
thanks
Thank you sir
Welcome
Please provide video 2 for free.We all will pray for your good health.Please sir we are students.
Dear, it is channel's policy
for 10 percent duty cycle apply and operation between clock and q1
For 10% duty cycle why can't we just give Q1 and clk to and gate
nice
Thanks
Your shift register is not initialized.
There is no obvious way it was initialized of 5'b10000 before.
It could be 5'b00000 or 5'b11111 after reset. The simulation of this will result in 5'bxxxxx.
How to make a 75% duty cycle.
1-Cycle difference -- 20% duty cycle
1/2 cycle difference -- 10% duty cycle
Q1_ff AND Q2 GIVE 10%DUTY CYCLE
This is one of the many options .. Q1 . Q1_ffn will also yield 10% duty cycle. But appreciate your understanding.
It should be Q1_ffn AND Q2