Відео

Thank you sir 👍

module ram_test; reg [9:0] address; wire [7:0] data_out; reg [7:0] data_in; reg write, select; integer k, myseed; // Correct module instantiation ram2 RAM(data_in,data_out, select, write, address); initial begin myseed = 35; // Move this inside the initial block // Writing to memory for (k = 0; k <= 1023; k = k + 1) begin address=k; data_in = (k + k) % 256; write = 1; select = 1; #2 write = 0; select = 0; end #2; // Small delay before reading // Reading from memory randomly repeat(20) begin #2 address = $random(myseed) % 1024; write = 0; select = 1; #2 $display("Address: %5d, Data: %4d", address, data_out); end end endmodule corrected testbench

shouldnt we show overall in case as in X=16'h0001; Y=16'hffff; //X=0000 0000 0000 0001, Y=1111 1111 1111 1111 At time 10 Z=0000 0000 0000 0000, C=1, S=0, Z=1, P=1, OF=0

Thank you very much Sirrrrr

6:5

at 19:40 shouldn't carry expression has (z&x) instead of (z|x)

Thank you sir .. This lecture series is much useful...for those who are starting now...at the begining u will be worried....just be patient and listen to him carefully...and must and must do a parallel practice in hdlbits....else you will be frustrated with the series.....thanku....must watch.....

How can i get notes for these lectures

Thank you, correct me if I'm wrong I think in 19:23 this is a Demux not a decoder since we have a selector

at 20:24 no monitor or display is used. How will get the waveform?

For T fip flop shouldn't we take T as one of the inputs?

A jewel series from past

Download the latest version of iverilog not the stable version if vcd file is not created by the command.

Thanks

14:13 the statement "bitwise operators operate on bits and return a value which is also a bit" is incorrect. because bitwise operators do not necessarily operate only on single bits, nor do they always return a single bit.

Always great full to the proff, best ever teacher for verilog. thankyou so much sir 🩵🩵

Is this course present in NPTEL courses..?👀

2024 and we hitting 3nm

brillant teaching

Notes of the these lectures drive.google.com/file/d/19nENrfyDvwPo9R-9kOMGKFWEKvtl03IO/view

guys,does anyone know ho to get the slides which prof explain?

someone 19:33

At 26:35, d_out and t should've been declared as reg variable since they are placed on the left side in an always blocks. showing that this is a behavioral simulation.

27:43 ( Branch Operation ) : if the cond == 0 only then send the ALUOUT to PC else if cond ==1 send NPC value to PC .

a genius thanks

how are writing to a register when we're reading it? like there is no logic in assign statement to dtop this is it fine?

sir which simulation tool it is?

is this ppt which used in all the vedios is available?

sIR i am using icarus verilog and getting the output i am getting R1 - 10 R2 - 20 R3 - 25 R4 - 4 R5 - 29 can somebody send the code

Detailed yet crisp lecture series covering such broad spectrum. Thank you sir for the valuable course. Hope more such will follow!

once in state 5 and the q0,q1 is 11 it will not leave state 5 because in the second always block we are looking out for state change and we not change out of state 5

at 29:57 , there is a mistake .....if zero is applied how can it make transition to two different states with applied input is same.

in last module "simple_latch", shouldn't 't' be of type 'reg' as it has been assigned inside 'always'?

In IF why we use pc+1

in 18:49, explicit association should be "<.> <ports_from_module>(<ports_from_testbench>)", anyone can notice and reply please

15:07 can't we achieve the same functionality using blocking assignment?

3:53 isn't 1^x = x' (x complement)?

6:34 In non blocking condition what will be the result when time delays are different

Thank you for this amazing series Sir❤

9:26 count has to be intialised to zero right??

in time 10:20 state diagram redundant states are there sir

Thankyou sir !!!

where we can download the notes??

I guess for the modified method, in last part you forgot to write next state =S1 and S2 in that 2nd always block

where can i get this ppt

17:00

28:00

in full adder circuit there is no 3 xor circuit present and some verilog code is not correct , please make new playlist

use delay #1 before display, soo that the input and output are settled before display. Now you will get correct Output.

14:40 Why did we use mux16 to1 M' instead of 'mux16to1 DUT'