MODELING MEMORY

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  • Опубліковано 12 січ 2025

КОМЕНТАРІ • 13

  • @sudhanshu1351
    @sudhanshu1351 2 роки тому +8

    At 25:42 you have written read which is not defined.

    • @phaneendrakumar658
      @phaneendrakumar658 7 місяців тому

      He even did not define data which is inside for loop

  • @StaliN_29
    @StaliN_29 Рік тому +1

    eg:4 of ram3 we do not declare any signal like read, why should we consider that "read_signal" in the ram_test,,why?????

    • @EzekeGakoni
      @EzekeGakoni 9 місяців тому

      I believe it's just a typo and it can be ignored. Earlier, prof said if write = 1, we write and if write = 0, we read.

  • @harshavardhankr7006
    @harshavardhankr7006 2 роки тому +2

    is the code given at the end correct?

  • @shubhurv543
    @shubhurv543 4 роки тому

    At 5:48 how can we use initial block inside a module...we can use initial block under test benches only I guess...

    • @pratikpawar5842
      @pratikpawar5842 3 роки тому +1

      We can use initial in module by knowing it's use. Initial will execute only once. And here we are storing data in memory so no need of always block. The thing is we can't use always block in testbench.

    • @StaliN_29
      @StaliN_29 Рік тому

      tell me the reason why shouldn't we consider, it because mem[i]'s are unpacked part selected bits, such that we shouldn't use the "continuous assignment" for those LHS="reg data_type" and RHS has value in binary formate we should use it, that's why with the use of procedural block and blocking statements we can write the mem[addr]=value;

    • @EzekeGakoni
      @EzekeGakoni 9 місяців тому

      When instantiating a memory module in a testbench, we may want that memory module to initially have stored certain values. Hence, for this to be the case each time we instantiate a memory module, we can initialize the memory locations using an initial block in the module.

    • @EzekeGakoni
      @EzekeGakoni 9 місяців тому

      @@pratikpawar5842 In pretty much all synchronous circuits, the testbench uses an always block for the clock?

  • @shruti-s2b
    @shruti-s2b 5 днів тому

    module ram_test;
    reg [9:0] address;
    wire [7:0] data_out;
    reg [7:0] data_in;
    reg write, select;
    integer k, myseed;
    // Correct module instantiation
    ram2 RAM(data_in,data_out, select, write, address);

    initial begin
    myseed = 35; // Move this inside the initial block
    // Writing to memory
    for (k = 0; k

  • @skanoun
    @skanoun 2 роки тому +1

    I love you prof

  • @rahultheytv5347
    @rahultheytv5347 5 років тому +1

    thank you for videos sir