For a free course on basics on verilog on sparten6 as well as eda, u can join here: dvrblacktech.pythonanywhere.com/Courses/verilog-handson-with-sparten-6-mini-course
For a free course on basics on verilog on sparten6 as well as eda, u can join here: dvrblacktech.pythonanywhere.com/Courses/verilog-handson-with-sparten-6-mini-course
For a free course on basics on verilog on sparten6 as well as eda, u can join here: dvrblacktech.pythonanywhere.com/Courses/verilog-handson-with-sparten-6-mini-course
1. For verilog on sparten 6 FPGA dvrblacktech.pythonanywhere.com/Courses/verilog-handson-with-sparten-6-mini-course 2. For basics of VLSI - analog design dvrblacktech.pythonanywhere.com/vlsi
Change the simulator on eda playground, make sure you clicked on show ep wave after simulation. Recently the simulator that I chooses in the left side list, is not working properly. So choose some other simulator tool and rerun.
On eda playground i guess its not possible to connect hardware and send code to FPGA. What you can do is, use 4 parking slots, for each slot attach one ir or ultrasonic sensor and connect one display to FPGA. Now in verilog code, simply read the input of all those 4 IR, sensors, if car is there is slot, ir will output 1, else 0, simply use if condition and display which slot is free or which slots are occupied..
Awesome explanation brother .... Thanks for making this video❤️❤️👌👌👌
For a free course on basics on verilog on sparten6 as well as eda, u can join here:
dvrblacktech.pythonanywhere.com/Courses/verilog-handson-with-sparten-6-mini-course
Awesome. You saved my assignment 😎
For a free course on basics on verilog on sparten6 as well as eda, u can join here:
dvrblacktech.pythonanywhere.com/Courses/verilog-handson-with-sparten-6-mini-course
thank you bro
your video is very useful
For a free course on basics on verilog on sparten6 as well as eda, u can join here:
dvrblacktech.pythonanywhere.com/Courses/verilog-handson-with-sparten-6-mini-course
You are awesome dude 👌👌👌👌👌
Hi sir your lecture is excellent.sir want i want front end vlsi document.tell how to download doc .plzz sir
1. For verilog on sparten 6 FPGA
dvrblacktech.pythonanywhere.com/Courses/verilog-handson-with-sparten-6-mini-course
2. For basics of VLSI - analog design
dvrblacktech.pythonanywhere.com/vlsi
Hi rohith, do you know how to do 3 bit counter?
// ROHIT D H
// 3 bit counter
module counter(
input clk,
input rst,
output reg[2:0]count
);
always @(posedge clk)
begin
count
Do you also know VHDL for a counter? Or do you do just verilog?
Actually I don't have any code, just wrote in comment, vhdl I don't know much yet..I think u can get vhdl on google
That's alright, thank you for replying
@@dvrblacktech bravo , this code useful for the beginner
Output is not coming sir
Change the simulator on eda playground, make sure you clicked on show ep wave after simulation.
Recently the simulator that I chooses in the left side list, is not working properly. So choose some other simulator tool and rerun.
Can you plz make video on car parking system using fpga on eda playground
On eda playground i guess its not possible to connect hardware and send code to FPGA. What you can do is, use 4 parking slots, for each slot attach one ir or ultrasonic sensor and connect one display to FPGA. Now in verilog code, simply read the input of all those 4 IR, sensors, if car is there is slot, ir will output 1, else 0, simply use if condition and display which slot is free or which slots are occupied..
Can You send me the code for Full Adder?
Full adder using 1 bit, a,b,cin,sum,carry
www.edaplayground.com/x/Vy9z
Full adder using 2 half adders
www.edaplayground.com/x/hMaX
Plz share the code sir
www.edaplayground.com/x/udJS
(Sorry for delay)