how to use modelsim for verilog code| modelsim working for half adder
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- Опубліковано 5 вер 2024
- modelsim for verilog | Modelsim software | half adder code in modelsim| how to use modelsim in English
how to use modelsim for verilog coding
how to use modelsim software for vhdl simulation
how to use modelsim for verilog
how to use modelsim
how to use modelsim in English
how to use tenchbench in modelsim
how to work on modelsim in english
half adder rtl coding
half adder testbench
While writing the tb of halfadder, unexpected error coming at the TB CODE closing of begin statement (end) there is no syntax error.
What should be the error?
I tried to find still no solution
@@sree_r4g_Please do as like same in video I explained..it will not come.
Will you post more videos on using verilog code it will be really helpful for poor students like me
Okay sure...I will post soon
mam how i can see the circuit diagram of half adder in modelsim
Here you can see waveforms
how to disable code folding on modelsim?