In the end of the presentation you have shown in halfbridge configuration there is negative voltage peak has seen ,but it can be eliminated using series resistor to save the driver. There is an alternative way to save that using TVS diode to clamp the negative transient, without inserting a resistor in the path....and than k you for your wonderful presentation as always.
Thanks for participation and contributing,. Indeed, the peak can be chopped but the purpose in video was to show the implication's when a resistor is added.
Thank you professor. Would be nice a video on configurable current mode MOSFET drivers, pros and cons, etc... I have used them sucessfully to tune the rise and fall time to make the system EMC compliant.
Great video, this help new people in energy electronics safe a lot of time. I have one question about gate charge circuit, many time I saw resistor between gate and source (most popular 10kohm). I thing this is useless element if we use dedicated driver for mosfet, but nice to know your opinion about this element.
Hi Marcin, thanks for participating. The function of the parallel resistor is to provide a low impedance, sort of ESD protection and bleeding of leakage current of gate. Indeed, when there is a driver it is supposed to provide the low impedance path. But...if the auxiliary power supply is off? the impedance might be high and EMI might turn on or even damage the gate. And more severely if one applies the high voltage to power transistor (with no auxiliary power to driver) ,the spike via the "Miller" cap might be a problem.
Incredible video! I have one question. When calculating the gate current, will it be more accurate to consider the Miller Plateau voltage instead of the threshold voltage?
Thank you professor, this is the best explanation about gate resistors in the internet. However, i have a question sir. How to determine the turn-on time to avoid the reverse-recovery? is there any range for that?
Reverse recovery is a function of the forward current and dI/d Hence, for a gives forward diode current the way to reduces di/dt. One way is by slowing down the turn on of the complementary transistor.
Thank you for your great work i think RG of mosfet(that write value in datasheet of each mosfet) must use for external resistor switch on and off true ?
@@sambenyaakov I think we must add RG in data sheet to external resistor that find with equation so If RG is 2ohm and we find Ron resistor 12, better use 10ohm in circuit and if for roff if find with equation 4ohm, good choise for roff external is 2ohm Ron(from equation)=Ron(external)+RG Roff(from equation)=Roff(external)+RG
@@sambenyaakov for range of RG I think better choose is take maximum resistor that write in the data sheet and add value to external resistor to achieve equation resistor
I now understand that by RG you meant the internal gate résistance. Strictly speaking you are right but in practice, the other inaccuracies make the precise calculation meaningless.
Hello, Prof. Are you suggesting that the threshold voltage of the FET and Miller plateau voltage of the FET are equal? In my limited understanding, the miller plateau voltage is greater than or equal to the threshold voltage.
Thanks for participation and input. The plateau is at voltage that needed to sustain the current during transition. Since the gm curve is rather fast rising the difference from Vt is small.
In some books it is written that the gate resistance is used to dampen the oscillations caused by the junction capacitance and the stray inductance. I am curious that how is the presented theory in harmony with this statement. Thank you
Thanks for bringing up a very good point which I have not covered in video. The problem of oscillation is in parallel the issues I have discussed and stems from the fact that the drive lines have a stray inductance. Resistance will dampen the oscillation if the quality factor Q is reduced to about 1 or below.
Hi Professor. I have one question during test in the labo when using Mosfet SIC NVHL160N120SC1 for the full bridge ; For the commad Vgs (-5V & 20V), during turn on, there is Peak Voltage found on the Vgs , which can be higher than 25V; So there is risk to destroy the Mosfet due to limited max 25V from the datasheet; I do the simulations and this peak voltage on the Vgs coming from the stray indutace of the pins of TO247 ( NVHL160N120SC1); My solution is to increase Rgon value to slow the switching on ; do you think is a good way? thanks
I do not think that the reason is inductance in package, probabely the traces. Yes, adding R reduces Q and hence damps oscillation - at the expense of a slower drive and higher switching losses.
Thank you professor for the video. I have question. How about putting the resistor only on the source pin? but not in the gate. ie at 19:34 remove the Rm and replace by Rson and Rsin.
Hi Profesor. In minute 13:43 you said (8-0.5)/1 give us 7A. But what with this 10R resistor?, he will not play in current value? If we will take large amount of current from this two capacitors, the have ESR and he will not decrease amplitude of current? As always thank you for very educational video
The capacitors start charged at 8V. That is why the 10R resistor is there - to charge them initially. So the initial current (8-0.5)/1 comes from the capacitors and goes down tending to ~(1.18-0.5)/1 = (8-1.18)/10, and in that case the current comes from the 8V supply. ESR could have an impact, but you can get good caps with ESR in the order of 0.1 ohm.
Thanks for participation. The pulse is short so the voltage on capacitor barely changes (ESR is small compared to internal resistance of driver). The function on the 10R is to charge/discharge the cap during the rest duration.
Hello professor, I have a question about this moment shown in the video ua-cam.com/video/Aq1Iw6ByXAw/v-deo.html. I understand that delta time refers to the voltage rise time of the VGS and not the fall time VDS. In the case where we assume the fall time for the voltage VDS, we will use the charge accumulated in the plateau region in the equation. Am I right?
I can only assume that you did not watch the video carefully. Why would you have a problem with a 7.2 Ohm resistance of the Rds(on) of the gate driver as given by the manufacturer and copied in the presentation, Clifford?
At 3:43 you say: (Paraphrasing here) "Before Q1 is turned on, Q2 was turned on. Current was flowing through Q2. Then, Q2 is turned off, and we start a dead time. This will cause Q2s parasitic diode to forward bias." If, Q2 was conducting, that means the switching node was positive (+HV). So when Q2 is turned off, the switching node will go negative to keep the current going in the same direction. That means Q1s parasitic diode with forward bias, not Q2s. We then proceed to turn on Q1 once the dead time is over. Could you help me out reasoning how Q2s diode get forward biased after Q2 is turned off? Wouldn't it be Q1s diode that forward biases?
"the switching node will go negative to keep the current going in the same direction." Not so. The current is maintained same direction by D2. To self commutate the mid point voltage you have to charge the parasitic capcitor with a current of OPPOSITE direction. Thanks for intertest. capacitors
Why this diode turns on momentarily when we turn on lower fet ? When upper fet is on this diode is reverse biased when lower fet turns on anode of diode is pulled down to ground so it’s still in reverse biased mode why it shows current peaking ?
Thank you so much professor. Its the best in the internet.
Thanks
Thanks a lot for your incredible work . May god bless and protect forever
Thanks for kind note.
Thank you professor!
Great presentation as usual 😊
Thanks
Thank you very much professor.
👍
It's an excellent video dear Prof. Thank you very much! Ofcourse, very eager to watch more such informative videos from your end.
Many thanks!
Very interesting! Thank you,professor !
Thanks Vladimir. How are you?
@@sambenyaakov Aefut mehahagim
))
Ty. Again very well explained.
Thanks
In the end of the presentation you have shown in halfbridge configuration there is negative voltage peak has seen ,but it can be eliminated using series resistor to save the driver. There is an alternative way to save that using TVS diode to clamp the negative transient, without inserting a resistor in the path....and than k you for your wonderful presentation as always.
Thanks for participation and contributing,. Indeed, the peak can be chopped but the purpose in video was to show the implication's when a resistor is added.
Thank
👍🙏
Helpful video 👍 I liked it
Thanks
Thank you professor. Would be nice a video on configurable current mode MOSFET drivers, pros and cons, etc... I have used them sucessfully to tune the rise and fall time to make the system EMC compliant.
Thanks for suggestion. Will consider.
🙏🙏🙏❤️🙏🙏🙏
👍😊
Great video, this help new people in energy electronics safe a lot of time. I have one question about gate charge circuit, many time I saw resistor between gate and source (most popular 10kohm). I thing this is useless element if we use dedicated driver for mosfet, but nice to know your opinion about this element.
Hi Marcin, thanks for participating. The function of the parallel resistor is to provide a low impedance, sort of ESD protection and bleeding of leakage current of gate. Indeed, when there is a driver it is supposed to provide the low impedance path. But...if the auxiliary power supply is off? the impedance might be high and EMI might turn on or even damage the gate. And more severely if one applies the high voltage to power transistor (with no auxiliary power to driver) ,the spike via the "Miller" cap might be a problem.
Hi Sam,
Thanks for respond. That nice to know, Thanks!
Incredible video! I have one question. When calculating the gate current, will it be more accurate to consider the Miller Plateau voltage instead of the threshold voltage?
When gm is high, as typical of power transistors, the threshold and Miller plateau voltages are about the same.
Thank you professor, this is the best explanation about gate resistors in the internet. However, i have a question sir. How to determine the turn-on time to avoid the reverse-recovery? is there any range for that?
Reverse recovery is a function of the forward current and dI/d Hence, for a gives forward diode current the way to reduces di/dt. One way is by slowing down the turn on of the complementary transistor.
@@sambenyaakov Is there any explanation about how much "slowing down" is sir?
Thank you Professor! Just curious why half the energy is lost during turn on?
See ua-cam.com/video/DlSmnEybrRE/v-deo.html
There are many more videos on the subject in my UA-cam channel
Thank you for your great work
i think RG of mosfet(that write value in datasheet of each mosfet) must use for external resistor switch on and off
true ?
But in many datasheets you are given range of Rg , so which one to choose?
@@sambenyaakov I think we must add RG in data sheet to external resistor that find with equation so
If RG is 2ohm and we find Ron resistor 12, better use 10ohm in circuit and if for roff if find with equation 4ohm, good choise for roff external is 2ohm
Ron(from equation)=Ron(external)+RG
Roff(from equation)=Roff(external)+RG
@@sambenyaakov for range of RG
I think better choose is take maximum resistor that write in the data sheet and add value to external resistor to achieve equation resistor
I now understand that by RG you meant the internal gate résistance. Strictly speaking you are right but in practice, the other inaccuracies make the precise calculation meaningless.
@@sambenyaakov thank you for good reply
i got it :)
Hello, Prof. Are you suggesting that the threshold voltage of the FET and Miller plateau voltage of the FET are equal? In my limited understanding, the miller plateau voltage is greater than or equal to the threshold voltage.
Thanks for participation and input. The plateau is at voltage that needed to sustain the current during transition. Since the gm curve is rather fast rising the difference from Vt is small.
In some books it is written that the gate resistance is used to dampen the oscillations caused by the junction capacitance and the stray inductance. I am curious that how is the presented theory in harmony with this statement. Thank you
Thanks for bringing up a very good point which I have not covered in video. The problem of oscillation is in parallel the issues I have discussed and stems from the fact that the drive lines have a stray inductance. Resistance will dampen the oscillation if the quality factor Q is reduced to about 1 or below.
@@sambenyaakov Thank you for the reply Prof.
Hi Professor.
I have one question during test in the labo when using Mosfet SIC NVHL160N120SC1 for the full bridge ; For the commad Vgs (-5V & 20V), during turn on, there is Peak Voltage found on the Vgs , which can be higher than 25V; So there is risk to destroy the Mosfet due to limited max 25V from the datasheet;
I do the simulations and this peak voltage on the Vgs coming from the stray indutace of the pins of TO247 ( NVHL160N120SC1);
My solution is to increase Rgon value to slow the switching on ; do you think is a good way? thanks
I do not think that the reason is inductance in package, probabely the traces. Yes, adding R reduces Q and hence damps oscillation - at the expense of a slower drive and higher switching losses.
Thank you professor for the video. I have question. How about putting the resistor only on the source pin? but not in the gate. ie at 19:34 remove the Rm and replace by Rson and Rsin.
There is a need for separate Ron and Roff for each transistor because parallel connection of MOSFETs is not desirable due to Vth spread.
BTW professor, are you sharing the presentations in PDF format somewere? thanks a lot!
No, sorry.
Hi Profesor. In minute 13:43 you said (8-0.5)/1 give us 7A. But what with this 10R resistor?, he will not play in current value? If we will take large amount of current from this two capacitors, the have ESR and he will not decrease amplitude of current? As always thank you for very educational video
The capacitors start charged at 8V. That is why the 10R resistor is there - to charge them initially.
So the initial current (8-0.5)/1 comes from the capacitors and goes down tending to ~(1.18-0.5)/1 = (8-1.18)/10, and in that case the current comes from the 8V supply.
ESR could have an impact, but you can get good caps with ESR in the order of 0.1 ohm.
Thanks for input.
Thanks for participation. The pulse is short so the voltage on capacitor barely changes (ESR is small compared to internal resistance of driver). The function on the 10R is to charge/discharge the cap during the rest duration.
Hello professor, I have a question about this moment shown in the video ua-cam.com/video/Aq1Iw6ByXAw/v-deo.html. I understand that delta time refers to the voltage rise time of the VGS and not the fall time VDS. In the case where we assume the fall time for the voltage VDS, we will use the charge accumulated in the plateau region in the equation. Am I right?
The time of the plateau IS the fall time of Vds
7:06
Why is the Vgs = Vt a crucial time for Ig calculation?
This is when the switching transition occurs
@@sambenyaakov is that the point at which Ig is at its peak? Why wouldn’t we calculate like: Ig = Vcc / Rsum?
@@bernard.tomasevic at this point the voltage of the gate is Vt, the peak current is when Vgs=0
How practical is it to find a 7.2 Ohm resistor, Ben-Yaakov?
I can only assume that you did not watch the video carefully. Why would you have a problem with a 7.2 Ohm resistance of the Rds(on) of the gate driver as given by the manufacturer and copied in the presentation, Clifford?
At 3:43 you say: (Paraphrasing here)
"Before Q1 is turned on, Q2 was turned on. Current was flowing through Q2.
Then, Q2 is turned off, and we start a dead time. This will cause Q2s parasitic diode
to forward bias."
If, Q2 was conducting, that means the switching node was positive (+HV). So when Q2 is turned
off, the switching node will go negative to keep the current going in the same direction.
That means Q1s parasitic diode with forward bias, not Q2s.
We then proceed to turn on Q1 once the dead time is over.
Could you help me out reasoning how Q2s diode get forward biased after Q2 is turned off? Wouldn't it be Q1s diode that forward biases?
"the switching node will go negative to keep the current going in the same direction." Not so. The current is maintained same direction by D2. To self commutate the mid point voltage you have to charge the parasitic capcitor with a current of OPPOSITE direction. Thanks for intertest. capacitors
Sir, during verification there is 10R resistor after 8V source. Why you didnt take 10R resistor into the consideration and divide it only by 1ohm ??
Sir inverter me Mospet k gate par kitne ohm ki regitance lage gi
?
Why this diode turns on momentarily when we turn on lower fet ? When upper fet is on this diode is reverse biased when lower fet turns on anode of diode is pulled down to ground so it’s still in reverse biased mode why it shows current peaking ?
Reverse current is during the dead time
@@sambenyaakov dead time is when both fets are off state .. so diode becomes forwards biased momentarily ?