Hi Zach, thank you so much for this great content. this is really important and I think this is true about removing NFPs on the inner layers of some HDI boards and we should consider the minimum Annular Ring(or more) as minimum clearance between VIAs barrel and other traces or planes in the inner layers.
Hi Altium Academy: Thickness Via plating is also important for the maximum current and this is different for different manufacturers. If the current is very high the solution is to place 2 or more Vias.
Yes definitely for power it is important, in fact I will probably need to do a video on routing through vias for power considerations in DC and high speed design.
I would not trust a board that doesn't have teardrops (or a designer that resists teardrops). Great video, as usual. I would add, try to go as big a via and pad as possible. 10 mil drill is OK but bigger is better.
Agreed, 10 mil is what I normally go with on smaller boards with smaller digital components that need to be packed close together. On other boards where the density is not a requirement I will go bigger than 10 mils.
Hi Zack! Could you assist with the metric system also? I know that it's more clear in imperial (mils), but some of us use metric system. (Before anyone says, there are conversion tools - yeah, I know - but it would be better to have it here; maybe even for comparison)
For outer layers the pad would be 18 mil minimum for Class 2 compliance when the manufacturer can guarantee the highest producibility level under IPC 2221 and IPC 6012. For class 3 it would be 20 mils. To keep it simple, you can use the same pad size on inner layers.
Yes of course, as long as the pad is large enough it will not matter where you route into the via. The pad needs to be large enough to ensure that the leftover annular ring after drilling leaves a copper connection to the trace. Some manufacturers will recommend teardrops be placed to ensure the trace will have enough extra copper so that a missed drill hit will not disconnect the trace from the via.
Hi Zach. For a 4-layer board. Going from L1 to L4 thru-hole... are the pads needed on the internal layers or only on the top and bottom? Sometimes Altium adds pads on all layers and sometimes it doesn't. Altium also allows you to change the pad diameter for the internal layers, for example to 0, is that allowed?. What are the issues with not having pads on internal layers for a thru-hole via?
Yes you can remove those pads on the internal layers. They are called "non-functional pads" and there is sometimes some debate as to whether they should be kept in the layout or whether they should be removed. The argument for removing them is that they can create a problem called "telegraphing" due to resin starvation around the the via hole wall. There is also the possibility of shorts when a trace is routed too close to the pad, either due to ECM failure or just due to fabrication tolerances, although modern CAD tools will flag a design rule error if you violate trace-to-pad clearances. I still need to do a video about this because it's an important reliability topic.
Hello, as you spoke about drill wanders can this be a tedious task for manufacturer to manufacture fine pitch BGA pads which uses vias in pads technology?
Sure it could be, but standard drill tooling and process can do it even if it's part of a BGA footprint. For BGA with via in pad, the other important aspect is fill and plate, which needs to be void free and not have large dimples.
This is a good question as I've heard arguments both ways. Technically no, if there are no tracks then you would not need the additional pads at all. The two main arguments for removing NFPs on internal layers are: 1) they reduce drill bit life because copper is harder to drill through than substrate, and 2) they create stress concentration along the via barrel. The 2nd point seems to be one of contention since people will say the via barrel is less reliable if there are no pads because the plating might separate from the hole wall. Then there is the signal aspect; vias with NFPs can have higher insertion/return losses. If you are going to remove NFPs you should do it after routing, or you should just leave them off and apply a larger hole wall to clearance spacing limit. That way, you reduce the risk of the drill hit touching a nearby trace and creating a short.
@@Zachariah-Peterson great response, thank you so much. I removed the NFPs so internal planes would have less discontinuities. I'll take more care with that approach now with the points you mentioned. Thank you
@@Zachariah-Peterson I find your content and detailed insights to be extremely helpful. Keep up the great work! On the topic of IPC standards, can you provide a comprehensive list of them that covers both DFM and DFA? Also would be great if you could provide links for download of the previous version if the latest version is not possible due to cost🙂
Uh, you're also wrong about process flow. See this - ua-cam.com/video/rLBChuikmGU/v-deo.html - - yea, inner layers are etched prior to drilling, but once they are stacked and pressed, the outer layers are then drilled PRIOR to exposure/development/etching. So once you've assembled the layers stacks (prepreg/cores) you THEN DRILL - then plate -THEN you do the photoresist and etch the outer layers. For one, if you tried etching first then drilling, the force of the fishtail carbide bits would most likely rip the via pads off. Two, having solid copper on the outsides allows for better plating.
Hi Zach, thank you so much for this great content. this is really important and I think this is true about removing NFPs on the inner layers of some HDI boards and we should consider the minimum Annular Ring(or more) as minimum clearance between VIAs barrel and other traces or planes in the inner layers.
That's a great point and I should have mentioned it in the video. I'm going to plan out a video on this for this week!
another video saved in "just in case" playlist
Thanks much for these helpful videos 🙏
Thanks a lot ❤ That's great as always ❤
Thank you! That was informative.
Glad you enjoyed it!
Hi Altium Academy: Thickness Via plating is also important for the maximum current and this is different for different manufacturers. If the current is very high the solution is to place 2 or more Vias.
Yes definitely for power it is important, in fact I will probably need to do a video on routing through vias for power considerations in DC and high speed design.
Super thanks ❤
Looking forward to seeing some quick tips in Altium in vivo, like the mentionet teardrops and more :D
Thanks maks886, we just finished filming a batch of these and more are in progress, including teardrops!
Super!!! Thanks!
I would not trust a board that doesn't have teardrops (or a designer that resists teardrops). Great video, as usual.
I would add, try to go as big a via and pad as possible. 10 mil drill is OK but bigger is better.
Agreed, 10 mil is what I normally go with on smaller boards with smaller digital components that need to be packed close together. On other boards where the density is not a requirement I will go bigger than 10 mils.
Hi Zack! Could you assist with the metric system also? I know that it's more clear in imperial (mils), but some of us use metric system. (Before anyone says, there are conversion tools - yeah, I know - but it would be better to have it here; maybe even for comparison)
Sure I'll try to include it where I can quickly do the conversion. However, once I start working in RF domain, I end up doing everything in metric!
So, if I use 10 mils diam hole, W should be 22 mils (min) for IPC-2221, right?
For outer layers the pad would be 18 mil minimum for Class 2 compliance when the manufacturer can guarantee the highest producibility level under IPC 2221 and IPC 6012. For class 3 it would be 20 mils. To keep it simple, you can use the same pad size on inner layers.
Can I know is it okay to place vias at the bending points of routing paths?
Yes of course, as long as the pad is large enough it will not matter where you route into the via. The pad needs to be large enough to ensure that the leftover annular ring after drilling leaves a copper connection to the trace. Some manufacturers will recommend teardrops be placed to ensure the trace will have enough extra copper so that a missed drill hit will not disconnect the trace from the via.
Hi Zach. For a 4-layer board. Going from L1 to L4 thru-hole... are the pads needed on the internal layers or only on the top and bottom? Sometimes Altium adds pads on all layers and sometimes it doesn't. Altium also allows you to change the pad diameter for the internal layers, for example to 0, is that allowed?. What are the issues with not having pads on internal layers for a thru-hole via?
Yes you can remove those pads on the internal layers. They are called "non-functional pads" and there is sometimes some debate as to whether they should be kept in the layout or whether they should be removed. The argument for removing them is that they can create a problem called "telegraphing" due to resin starvation around the the via hole wall. There is also the possibility of shorts when a trace is routed too close to the pad, either due to ECM failure or just due to fabrication tolerances, although modern CAD tools will flag a design rule error if you violate trace-to-pad clearances. I still need to do a video about this because it's an important reliability topic.
@@Zachariah-Peterson Appreciate your reply, love the videos and your professionalism very much.
Hello, as you spoke about drill wanders can this be a tedious task for manufacturer to manufacture fine pitch BGA pads which uses vias in pads technology?
Sure it could be, but standard drill tooling and process can do it even if it's part of a BGA footprint. For BGA with via in pad, the other important aspect is fill and plate, which needs to be void free and not have large dimples.
If a via has no internal layer tracks connecting to it, does it need internal pads at all?
This is a good question as I've heard arguments both ways. Technically no, if there are no tracks then you would not need the additional pads at all. The two main arguments for removing NFPs on internal layers are: 1) they reduce drill bit life because copper is harder to drill through than substrate, and 2) they create stress concentration along the via barrel. The 2nd point seems to be one of contention since people will say the via barrel is less reliable if there are no pads because the plating might separate from the hole wall. Then there is the signal aspect; vias with NFPs can have higher insertion/return losses.
If you are going to remove NFPs you should do it after routing, or you should just leave them off and apply a larger hole wall to clearance spacing limit. That way, you reduce the risk of the drill hit touching a nearby trace and creating a short.
@@Zachariah-Peterson great response, thank you so much. I removed the NFPs so internal planes would have less discontinuities. I'll take more care with that approach now with the points you mentioned. Thank you
I didn't see a link to the blog that also has links to getting the IPC standard.
Good catch, I added the link!
The current version of standard IPC-2221B is sadly not free.
@@robertdixon8238 Yes that's right, I provided 2221A in the blog.
@@Zachariah-Peterson I find your content and detailed insights to be extremely helpful. Keep up the great work! On the topic of IPC standards, can you provide a comprehensive list of them that covers both DFM and DFA? Also would be great if you could provide links for download of the previous version if the latest version is not possible due to cost🙂
@@RWCARC That will take some time to compile but I will do my best!
One of the reasons for higher cost vs smaller drill is due to dwell time...
Uh, you're also wrong about process flow.
See this - ua-cam.com/video/rLBChuikmGU/v-deo.html - -
yea, inner layers are etched prior to drilling, but once they are stacked and pressed, the outer layers are then drilled PRIOR to exposure/development/etching. So once you've assembled the layers stacks (prepreg/cores) you THEN DRILL - then plate -THEN you do the photoresist and etch the outer layers. For one, if you tried etching first then drilling, the force of the fishtail carbide bits would most likely rip the via pads off. Two, having solid copper on the outsides allows for better plating.