@@chraffis Yeah because Jon is known to never insert any jokes or puns inside his videos… Come on guys, CD/DVD/BR are still well-known we're not talking about cassette tape or floppy here.
It's obviously a joke. As a millennial I always hated the sneers boomers used to give while saying "bet you can't figure out this cassette tape or floppy disk" bruh I still used them when I was a kid. And I bet you if you gave them to a zoomer they'd figure it out too, it's not rocket science, they're just consumer objects. Now if someone asked a zoomer "how" those technologies work then yeah the average would not be able to answer, but neither would older generations. Average person doesn't even know how the technology they use every day works.
I worked at ASML when the first notions of NIL came around. Even wrote a few, now useless, patents around it. But still. I must admire the tenacity of the Canon people to regain some of the edge they used to have over ASML, technologically. As far as ASML goes, we rather quickly discarded the idea due to many of the impracticallities you mention.
I am former student of Prof. Stephen Chou. It is so good to see NIL is being introduced in such informative yet easy-to-understand way to the public. Kudos for the amount of work that Asianometry put into making this video.
Don’t ignore the optical applications. From what I understand all the AR glasses need specialized diffractive structures to project the image over a transparent glass. Stamping is currently used for this. The problem is these diffractive structures have funny angles and shapes so it’s much harder than semiconductor patterns, even if it’s larger.
I've always admired Canon. The things they innovate and have innovated is sometimes mind blowing. Damn shame SED (Surface Emission Display) tech, initially a joint venture with Toshiba, never made it, those displays were superior to both plasma and LCD of the time, massively superior. The contrast ratio is even nowadays unmatched, true 1.000.000:1 (Exception maybe OLED). It was actually a matrix of tiny electron guns with phosphors, combining the best of CRT and LCD. There were a handful of prototypes produced, but I've never ever seen anything about them, while I cannot imagine they would have been trashed. Anybody here who has had an SED TV prototype?
I seem to remember that Toshiba sold their portfolio to a patent troll famous in the West District of Texas which doomed the technology to the scrap heap.
@@brodriguez11000 Yeah, nice one! Maybe a whole vid on the history of SED overall, including the involved tech. "How a superior technology was destroyed by patent trolls"
@@lance31415 Yeah shitty way for a superior tech to die. That said, by the time SED was buried forever, OLED had made some progress. Which is even more efficient than SED was, but I think the CRT diehards would have been drooling over SED picture brilliance with the same phosphor bloom as CRTs had.
Nice academic review of NIL. From someone previously working in the semiconductor capital equipment industry for decades including working for Nanonex (by the way, pronounced the same as the other Steve). Discussions with leading litho folks at Intel, Micron and TI back in the day clearly shined light on the unlikely possibility NIL would ever become mainstream technology particularly due to direct contact mask defect issues. At the end of the day, MII likely would have never received another funding round and Canon was no longer relevant beyond the 193 nm dry steppers - a distant third. Canon needed new tech to provide an alternative to ASML or even Nikon. Remember, NIL is a JUST a fancy version of stamping or embossing.
I recently saw a startup demonstrate their ability to print semiconductors at the 2 and 3 nanometers scale using this technology, the question will be whether or not they can get yields and Purity high enough for this to be a competitive alternative to traditional euv lithography. If so, this could be a revolutionary change in the semiconductor manufacturing business that would completely change economies of scale
@@brodriguez11000It is already the printing industry way. The modern printing industry uses lithography technology not the imprint technology use in Gutenberg prints.
@@kazedcat The modern printing industry has also changed massively, with the classic printing method replaced by laser toner printing via photo sensitive drums. No more lithography needed, just direct digital raster data output to the printing device via a Raster Image Processor (RIP).
@@paulmichaelfreedman8334 Are you sure we are talking about the same industrial service? because AFAIK the massive offset printing industry doing books, posters, newspapers, labels or packaging still uses ink through the lithography technique.
well done as usual, i expect nothing but a top notch presentation from you all the time now, we have all gotten use to well researched and presented video's on various topics, but a lot on chip production, i cant think of anyone else that makes these video's on these topics so clearly presented, well done !!!
I was curious when NIL was in the news a while back and then kind of forgot about it. I thought this can't possibly work. Both due to the issue of alignment and the issue of keeping the mask defect free. So it turns out the first issue can be solved through looking through the transparent mask and the second issue can (maybe) be solved by just keeping the mask clean. I'm still skeptical because it sounds like an insanely difficult problem, but then I remind myself that everything in semiconductor manufacturing is insanely difficult and done against all odds.
@@GameboygeniusIt's not economically unviable just economically not competitive. The issue is throughput but as the EUV tech becomes more and more expensive with hyper NA and quad patterning there should be a crossover point where nano imprint becomes competitive. NIL's yield issue is independent of resolution but EUV's yield becomes more problematic as you shrink the features.
Even though you can look through the template, overlay is not a problem that’s going to go away because rather than adjust the image of the mask (which can scale linearly), changing the shape of the imprint template is limited by the modulus response of the template: a decidedly non-linear process. This means when you apply a correction to say, X-mag, different areas of the template will respond completely differently. Nano imprint is cute for some niche applications but it will never be used to print anything at the bleeding edge where its resolution capabilities shine. And on top of that, it’s slower than molasses in January.
The whole "young people don't know about tapes and CDs" is weird AF. Like, I was born at the tail of the 70s. And I know about wax cylinders and shellac 45s. So either young people are dumb as posts or it's all complete bullshit. I really hope it's bullshit or it ain't looking good for the species. It's probably bullshit.
The problem is not who takes over whom. But it is the perspective of industry. TSMC does chip maker work for any fabless semiconductor design while the Japanese do for themself.
The first time I've heard of nanoimprint lithography was about twelve years ago when Toshiba Machine developed a process for imprinting photonic crystal lattices on a GaN-on-sapphire wafer for improving the performance of blue LEDs. The process involved molding the structures into a plastic film and then using this film to imprint the structure into the resist. I believe they successfully commercialised that process.
You need to build your dad a Cantonese Spotify playlist. My mom bumps 70’s and 80’s Spanish ballads à la Julio Iglesias. Super syrupy tunes, but she’s super happy with them.
Syrupy, eh. My mom on the other hand doesn't like ballads like that and had a different liquid food related analogy to describe them. The music is so greasy that oil is dripping from the speakers.
So fascinating! Template replication is very reminiscent of how the production of physical music media works, with 1 master record/tape being used to create multiple clones. Hopefully this technology can find a place in the industry, even if it isn't on the leading edge.
18:25 alignment of 1nm. There Jon said that that is 10 atoms wide which is correct. Just more info, it doesn't mean about 10 atom distance inside material (eg. silicon, gold, etc). Approximately, two atoms inside nearly any materials is about 0.3nm. Means they can align within 3 atomic distance. Imagine like chocolate chip cookies. Chocolate chips size is smaller than distance between individual chocolate chips.
These lithographic techniques just get more and more like black magic all the time - wouldn't surprise me if they announced that there were better platter yields during the dark of the moon, or if the chanting of the heart sutra played in the background didn't give higher definition of the ICs.
I think nano imprint can work well with backside power delivery side of the semiconductor, it is only one or two materials copper and the insulation materials, as the purpose of this layer is solely for power delivery it is more simple and easier to work with, using EUV to this layer sounds like a match. Secondly, since you needed to sand down the backside to expose the nTSV, the canon material sound like they can align things before printing, which is like a perfect match, if things does fall off and created a hole in the backside, if the Canon machine can find the hole and place the correct amount of filling material and applied a pure flat mask to stable the backside before building the copper at the back can improve yield. Third, because the thing is self alignment, it also solves the possible misalignment, ie you only printed to the area you find the nm shifting if the dots from the exposed nTSV shifted 0.5nm to the left then the mask can shift left 0.5 as the machine naturally scanned what is the previous continuous print it can be just as easily to scan where these dots are and realign accordingly. If this is the case nano imprint naturally have advantages over EUV on the backside power delivery builds.
This makes clear that a big advantage of photolithography is the ability to reduce the image cast by the mask: nanoimprint lithography is by definition 1:1 so there has to be some way to create features at the desired size already. Photolithography has been able to bootstrap itself down to truly tiny sizes while also being commercially viable.
Perhaps with the integration of chiplet designs, they can print "easy" or "smaller" chips and by stacking them like what AMD does with their chips, maybe you can "build" your chips that way.
It would be much more interesting if they managed to make the first trailing node cheap as fuck. Most people, companies and institutions don't need the very best. The second best at a fraction of the price is often a very sweet proposition.
Actually I think this technology could work fine for magnetic disk drives. For what you said, terms like HAMR and PMR, PMR is simply how the spots are laid out on the disk surface and I don't see what this technology wouldn't work. It's just a pattern for how a SINGLE magnetic blob lays on the disk surface in relation to the other ones. PMR has a byte of spots in parallel so that as the disk is spinning under the read/write heads, instead of reading a single bit like the olden days, the heads are reading a byte at the same time (8 bits, or 8 magnetic spots). Now, the patterns have gotten more complex to increase bit density on the disk and it also means reading/writing is faster. HAMR is simply a technique involved in writing DATA to the spots, so that's not about a manufacturing process, that's about the operation of the device. In this case it's best to cover hard disk technology because this is a topic in itself. But I don't see why the nanoimprint tech can't be used for adding the magnetic dots to the hard disk surfaces. However, disk surfaces are expected to last MANY years so it is a highly technical process.
This technology harkens back to the methods used to reproduce not only CDs, but also phonograph records. Can we reach further back than that? Could one pattern the resist with gravure? There would be something wonderful about creating high-technology circuits with a process once used by Dürer and Rembrandt.
I have my doubts about the production of CDs with this method, as I have "burned" CDs(CD-R) with a computer. And the CD is an optical data ... wikipedia: "The compact disc (CD) is a digital optical disc data storage format " Put L(ong) P(lay)/ Vinyl records for sure are printed/imprinted.
@@jarnomikkola8438 When replicated in volume, CDs are pressed, like records, as Jon describes. So, for that matter, are DVDs and Blu-Ray discs. Readable and R/W media are a completely different process.
Mass-produced CDs are printed with a stamp. A CD has little pits to denote a bit. You can also create these pits using a laser (when burning a CD-R).@@jarnomikkola8438
@@fleetingfacet Time is a different dimention from width, lenght, and hight, because you have to program the printer head to actually print the different forms in a timed schedule, as they won't just appear from no-where.
If I was billionaire or banking firm. I'd be flying to Canon HQ and want in depth presentation on Canon NIL. If the last section of video is accurate. Anything that challenges status quo in lithography is going to be big (in end game of Moores Law).
An ex-Canon guy was just talking about this last week inside the fab and I thought, “ok if this is true, there will be an Asianometry video about it! ☝🏼”
The entertaining thing about picoliter droplets from Inkjets for JFIL is that's not even very expensive. Epson photo printers have been doing 3pl droplets for about 20 years now.
When the mask is removed your figures show resist material remaing in the spaces between the main pattern on the surface of the substrtate. I think it would be useful for viewers not familair with processing if you accounted for the dispostion of that material, in order to accurately etch the surface of the substrate below without damage or loss of shape of the main lithographic resist pattern.
NIL sounds like it would be a perfect match for making power electronic chips which need larger process features. EUV is great for leading edge, but we need more of these trailing edge machines.
Few days ago when I read about this in the news, i was thinking Asianometry needs to do an episode on it cuz only you can explain all the complexity involved so clearly and make it understandable.
We need some competition in the lithography machine market. ASML is the monopoly of high-end lithography machines for cutting-edge nodes. If Canon can bring the heat and drive down prices, then we might get better pricing for finished products.
NIL seems like the perfect choice for lower cost startup fabs and interposers in general, masks can be much larger and dust + mask durability isn't as much of an issue at 20-40nm feature sizes.
I think a video talking about masks would be a great thing. I don't think people realize just how hard it is to make a mask. For instance my understanding is TSMC takes a few days to make a mask for something like a CPU core die. In the part of inspecting a mask I was wondering if AI could be a great help here, I think it SHOULD. Nvidia has developed the AI software to help TSMC make masks and it's supposed to reduce the time down to less than a day if I recall the article correctly. TSMC has to of course BUY the system but I think it makes economic sense to do from many days down to a day and on top of that reduce the equipment to about 1/3 in the compute side to make it. And this uses AI. If you've made a video in the past maybe it would be good to cover what Nvidia is doing and how that can benefit companies like TSMC. A side note, throughput on these machines isn't just about the cost of the machinery running a production line. Actually that wouldn't even be the main point. If the machines are incredibly reliable over many years, ROI comes into play. No, it's more about the cost to RUN the line, so power consumption, maintenance based on run time, etc..... If it costs a company very little to run a line production can be slower and this should make sense. However a company has commitments so they have to meet a throughput that allows them to be profitable and meet their customer's needs.
Reliability is insignificant because of plan obsolescence. It does not matter if the tool last for 30 years when the shelf life of the technology is only 5 years. Yes you can fab 5nm process until 2033 that does not help you when the industry has already move on to 0.8nm.
@@kazedcat No that's not true. First you mean 1.8 because the node path is 3nm which TSMC is on right now, then 2nm, then 1.8, then 1.7, etc..... MAYBE by 2033 fabs are at 1.7, probably 1.8 because it's getting harder to move to each progressively smaller node. But nodes are just a name. TSMC's N3 isn't at the density they said they would be at so even with the fake naming scheme the lead company isn't making its goals, so it's N3 is really about what N4 should have been. Really. Go read. High-NA EUV is supposed to help get them back on the path of smaller nodes, as in REALLY SMALLER nodes, not just in name only. The companies have to get good at using the new lithography though and that takes about a year. But next is an assumption that the leading node is where all the business is and that's PURE fallacy. The fabs get a good 5 years out of the leading edge, and that means heavy business by companies making high end compute products, or Apple. What's going to happen is the nodes in the realm of 20 - 5 will start to replace most of the older nodes and that's because costs for materials are going back up, Something that may have been on nodes like 28 and larger will fade away and these newer nodes will replace them. You do hit a point where shrinking analog circuits isn't so great but you still get scaling down to about 6nm. But we're heading for a technology war between China, Russia, N Korea, Iran and a few other insignificant countries and the free world, or mostly free world, and materials used to make ICs INCLUDING silica, which becomes silicon are going to go up in price as China decides to greatly reduce what it sells, and they control the market of many of these materials including silica, which means even making those large crystals are going to get more expensive. So they'll be much more pressure on cutting the use of materials which will close a lot of those older fabs which means ever smaller nodes will become general purpose nodes. You know when AMD started using TSMC N7? 2019. Do you know AMD is STILL making products with N7? So even with just AMD alone TSMC is 5 years on a node that they started producing products with in 2016. Maybe what you don't realize is companies like AMD, Intel and Nvidia make a new generation of products over about 1.5 - 2 years as a NEW generation. But if that generation is successful they'll keep making that product. AMD will keep making Zen 3 and RDNA 2 graphics (6000 series) into 2024). They've continued to make those products as low cost products vs. their new line of Zen 4 and RDNA 3 graphics. Zen 2 was the first gen AMD CPUs to use TSMC N7. So here it is coming up on 2024, TSMC has been making products on an N7 process node since 2016 and they're STILL pumping out lot of products for different companies on that node. This stuff stays in production at a very profitable rate for the fabs for more years than you think, even making high end compute products.
@@johndoh5182 You don't know how to count you shrink around 30% per generation. So 3nm then 2nm then 1.8nm then 1.2nm and 0.8nm assuming the rate of 2 years per full node shrink will continue then at 2033 we will be at 0.6nm. I am accounting a slow down so 0.8nm in 2033 is a good prediction.
@@kazedcat Hey thanks for the insult shit head. I was polite with my comment, this will be my last and we'll agree to disagree. Roadmaps for process nodes have changes so many times it's ridiculous. At one time Intel showed a process map going from 20A to 14A. Yeah they changed that a couple years ago and in 2023, and it's hard to find and same is true with TSMC, finding a projected roadmap for more than about 2 steps, Intel shows 20A, then 18A, then 17A. Now, considering both TSMC and Intel are both WAY behind their roadmaps they published around 2019, 2020, I'm going to stick with what I said. There has ALREADY been a big slowdown. Intel was supposed to be on Intel 4 a couple years ago, and right now all they can do for NEXT year is put out laptop parts on it. Same thing happened to them moving to their node formerly know as 10nm, now called Intel 7. It's going to be 2025 when Intel has desktop parts out on Intel 4. That's FOUR years going from Intel 7 to Intel 4. It's POSSIBLE Intel may try to skip Intel 3, or they may still try to develop Intel 3 but maybe using High-NA to get to Intel 3 BEFORE they move to Intel 20A. But they have clearly published THIS year that their steps after 20A is 18A and then 17A. Then next projected step would be Intel 14A, but they're not publishing this in formal roadmaps that they release to their board of directors. They dropped everything below 18A. If you think these companies will magically get to something below 1 by 2033, fine with me. It's not happening but sure thing bud. And no there is no MAGICAL percentage that nodes shrink each gen. There is something that Intel, Samsung and Intel WANT to do, but that doesn't mean they have, and TSMC N3 is a perfect example of that. Once again YOU do the reading. Don't read anything older than 2023 though because that's what you did to come up with the numbers YOU did. This is from THIS year: "Anyway, the bottom line here is that some critical elements of TSMC's N3 and Intel's 4 nodes are looking very, very similar. Both TSMC's and Intel's high performance logic cells clock in around 125 million transistors per square millimeter. There are other chip elements from both manufacturers that will exceed that density. TSMC's N3 node will extend all the way to 215 million transistors per square millimeter. " This means at BEST TSMC is about 25% vs. N5. But of course here you have to understand that a process node comes with different libraries, with one being a typical low density library and another being a high density library. So here is the real truth. In use cases such as hi performance computing where clock speeds are as fast as possible, neither TSMC or Intel low density libraries have kept that pace. Also, Apple is frustrated right now with TSMC N3 because it's not meeting its production demand because the defect rate has been high. So once again, the rate at which these new nodes are coming is longer. AMD was supposed to have RDNA 4 and Zen 5, both coming out next year, on TSMC N3. That's been pushed back to some products on N4 and other products on N3. Considering NO company can really start work yet on a 2nm process UNTIL they have ASML High-NA equipment, I don't expect to see 2nm (once again a meaningless term) until 2026 because it takes a LONG TIME to develop these nodes. Intel is supposed to get a first delivery at the end of this year. They SAY they'll have 20A by 2025. Considering they're about 1.5 - 2 years late on their nodes for the last 3 nodes including the unreleased Intel 4, I'll make the call now, 2026 or 2027. TSMC will get High-NA in 2024. They've been better at getting nodes out but they've still struggled with both N5 and N3 both being behind, I'll say 2025 they MIGHT have their first run with Apple, who is always first on a new node once it's good enough for production. But really, that's what you want to talk about when you're first point was how many years a new node will have GOOD rates of production on it??? And you're wrong there too? And I didn't even give a complete picture on a new node. First run will be with risk partners. APPLE falls into that category. That's about 1 to 1.5 years depending on different factors. Then the NEXT group of chipmakers gets on that node. That doesn't mean Apple is no longer on that node though. AMD is NEVER on a first run for TSMC because they make critical components not just for consumers but also enterprise, so they are on the NEXT run. They could have 1 or 2 generations of products on that node. So this is high end computing, on a node that came out and was already in production before a company like AMD trusts it enough to use. Following the customers like AMD are OTHER customers that make components for computing. So you basically have THREE waves of chipmakers progressing through a node, and if a company like TSMC has a delay, those 3 waves can be many years. But once again, most companies don't just DROP product lines after a single run. They could be producing a line of products for 3 - 4 years. So yes, a single node or generation of nodes since there are variants of the same node can have solid production for about a decade. Over, OUT.
@@kazedcat you seem to be pretty misinformed about how semiconductor nodes are used. Right now, hardly any of a wafer uses leading edge nodes. Most of the semiconductor is still produced using older techniques. This has to do with yields and cost efficiencies. There are certain parts of a finished product that are best made using cutting edge tech, but the majority of it is produced using a gen or two older tech. I work in a leading edge semiconductor fab and we still have plenty of litho tools that are 10+ years old. Also, process node names/sizes are mostly meaningless nowadays. You're using those terms like that relate to physical transistor size, which they don't, and has been repeated on this channel dozens of times. You're quoting numbers that don't really have any meaning. Johndoh explained this to you pretty well and you seem to have ignored his explanation. So just to recap, you don't make a semiconductor out of one process node. You use a variety of nodes to produce a single product. The majority of those nodes are not leading edge. This is especially true with new chiplet designed products.
Carbon assembly using X-rays. Can hit resolutions down to 1nm, and thus can build essentially indestructible masks, or as close to it as possible as the structure is cubic in form, which is the strong arrangement of carbon known as diamonds. Currently only De Beers owns a lab doing this, as far as I know. The process is still unrefined and messy, but I am certain that it can build masks for this process.
NIL for rapid production of the higher metalic layers, with traditional processes for the transistor fabrication? - feels like physical lithography would be better for larger features..
This NIL reminds me that Lithography for an optical technology is actually a misnomer. Lithography means drawing with stone, the origin of steppers is put a pattern on a stone and then stamping or transferring this pattern to the will be chip. As such this NIL seems more like the historic way to produce chips.
If you can make the machine 10 times cheaper than an EUV machine, then you don't need equal throughput, individually. Just have more machines. Cool, I haven't keep up with the developments on this since 2006. NIL might be good for smaller chips or maybe FPGA. Ah, you mention memory chips at the end.
This doesn't scale perfectly in practice as fab real-estate is a recurring issue. Not that EUV don't have them, especially on the non-cleanroom floors of the fab.
The original machine had a base-plate of prefabulated aluminite, surmounted by a malleable logarithmic casing in such a way that the two main spurving bearings were in a direct line with the pentametric fan.
Creating the mask on Nanoimprint lithography, in the most important process of improving producing wavers on EUV Lithography. To big to develop yourself, the mask quality was the biggest problem, joying ASML was a smart move.
I assume that the equivalent of a resin printer that uses a higher resolution display as the equivalent of the template isn’t. But one wonders if further developments of high resolution displays couldn’t eventually replace some of of these technologies, maybe not at the smallest size, but very small sizes?
Why not replicate enough templates to allow for an entire wafer to be produced in parallel all at once? That would be a major multiplier in terms of speed and hopefully reduce costs/prices.
![Lp. Сердце Вселенной #60 РОЖДЕНИЕ ЛОЛОЛОШКИ [Финал] • Майнкрафт](http://i.ytimg.com/vi/YoR0pAV9FVQ/mqdefault.jpg)
This is the video I've been waiting for ever since I saw the headlines.
yes!
@@derekbrotherton3462lol then why are you here 😂😂
SAME
Same here!!
The fact that you had to explain what the CD is for younger viewers made me feel like a fossil
LOL Yes
Agreed. I actually came down here wondering if he was maybe joking or not.
He was 100% joking.@@chraffis
@@chraffis Yeah because Jon is known to never insert any jokes or puns inside his videos… Come on guys, CD/DVD/BR are still well-known we're not talking about cassette tape or floppy here.
It's obviously a joke. As a millennial I always hated the sneers boomers used to give while saying "bet you can't figure out this cassette tape or floppy disk" bruh I still used them when I was a kid. And I bet you if you gave them to a zoomer they'd figure it out too, it's not rocket science, they're just consumer objects.
Now if someone asked a zoomer "how" those technologies work then yeah the average would not be able to answer, but neither would older generations. Average person doesn't even know how the technology they use every day works.
Asianometry videos truly are some of the most fascinating videos on UA-cam.
I worked at ASML when the first notions of NIL came around. Even wrote a few, now useless, patents around it. But still. I must admire the tenacity of the Canon people to regain some of the edge they used to have over ASML, technologically. As far as ASML goes, we rather quickly discarded the idea due to many of the impracticallities you mention.
Saw this news... was hoping you;d make a video on it soon. Within HOURS you have uploaded it. LOVE YOU!
You did the VCR and VHS episode. You know you have to do CD, DVD and blu-ray now! Don't leave us hanging!
I am former student of Prof. Stephen Chou. It is so good to see NIL is being introduced in such informative yet easy-to-understand way to the public. Kudos for the amount of work that Asianometry put into making this video.
I'm an engineering student in my early twenties. You cover topics that my professors fail to recognize or even have the capacity to explain.
That is why they are your profs. They are on the way out while YOU are on the way UP!
That why you don't need styutent roan to make yu successful. Just you know what are doing.
What engineering? Don't expect first degree mechanical, civil, and chemical engineering courses to have it...
That's because your professors know you are not capable of understanding this.
I mean maybe its not what they are specialised in, also this is ATLEAST a masters if not phd level@@michaelrmurphy2734
Don’t ignore the optical applications. From what I understand all the AR glasses need specialized diffractive structures to project the image over a transparent glass. Stamping is currently used for this. The problem is these diffractive structures have funny angles and shapes so it’s much harder than semiconductor patterns, even if it’s larger.
I've always admired Canon. The things they innovate and have innovated is sometimes mind blowing. Damn shame SED (Surface Emission Display) tech, initially a joint venture with Toshiba, never made it, those displays were superior to both plasma and LCD of the time, massively superior. The contrast ratio is even nowadays unmatched, true 1.000.000:1 (Exception maybe OLED). It was actually a matrix of tiny electron guns with phosphors, combining the best of CRT and LCD. There were a handful of prototypes produced, but I've never ever seen anything about them, while I cannot imagine they would have been trashed. Anybody here who has had an SED TV prototype?
I seem to remember that Toshiba sold their portfolio to a patent troll famous in the West District of Texas which doomed the technology to the scrap heap.
Maybe he'll do a video on the nanoscale vacuum-channel transistor (NVCT) since miniaturizing tubes is the cool thing.
@@brodriguez11000 Yeah, nice one! Maybe a whole vid on the history of SED overall, including the involved tech. "How a superior technology was destroyed by patent trolls"
@@lance31415 Yeah shitty way for a superior tech to die. That said, by the time SED was buried forever, OLED had made some progress. Which is even more efficient than SED was, but I think the CRT diehards would have been drooling over SED picture brilliance with the same phosphor bloom as CRTs had.
I am lucky enough to do a lot of work with very high end Canon equipment. It easily my favorite and the same for everyone I work with.
this guy is pure gold!
Thank you for all your dedication, thought and humour when crafting your shows. A pleasure to hear and learn.
Nice academic review of NIL.
From someone previously working in the semiconductor capital equipment industry for decades including working for Nanonex (by the way, pronounced the same as the other Steve). Discussions with leading litho folks at Intel, Micron and TI back in the day clearly shined light on the unlikely possibility NIL would ever become mainstream technology particularly due to direct contact mask defect issues.
At the end of the day, MII likely would have never received another funding round and Canon was no longer relevant beyond the 193 nm dry steppers - a distant third. Canon needed new tech to provide an alternative to ASML or even Nikon.
Remember, NIL is a JUST a fancy version of stamping or embossing.
"...not the only step in the process. The test and metrology guys send me passive-aggressive emails to remind me.." 😂
I felt seen.
_Clicks reply_
"I'm not sure weather prediction has much to do with lithography"
LOL @@MostlyPennyCat Yah! i bet the meterologists are getting burned for no fault of their own 🤣
@@zeframm CD-Sem Matters!!
Really like the topical videos with cutting edge tech
I recently saw a startup demonstrate their ability to print semiconductors at the 2 and 3 nanometers scale using this technology, the question will be whether or not they can get yields and Purity high enough for this to be a competitive alternative to traditional euv lithography. If so, this could be a revolutionary change in the semiconductor manufacturing business that would completely change economies of scale
Making semiconductors the printing industry way.
@@brodriguez11000It is already the printing industry way. The modern printing industry uses lithography technology not the imprint technology use in Gutenberg prints.
What startup?
@@kazedcat The modern printing industry has also changed massively, with the classic printing method replaced by laser toner printing via photo sensitive drums. No more lithography needed, just direct digital raster data output to the printing device via a Raster Image Processor (RIP).
@@paulmichaelfreedman8334 Are you sure we are talking about the same industrial service? because AFAIK the massive offset printing industry doing books, posters, newspapers, labels or packaging still uses ink through the lithography technique.
well done as usual, i expect nothing but a top notch presentation from you all the time now, we have all gotten use to well researched and presented video's on various topics, but a lot on chip production, i cant think of anyone else that makes these video's on these topics so clearly presented, well done !!!
Dude this is a great account, have watched most of your videos. Thanks.
It's a tech dudes ASM -L- R
Lol. Just a few hours ago I emailed asianometry recommending production of a video covering these very issues. Very quick work!
Excellent video. I didn't even know this lithography process existed. This channel is a goldmine.
yeah he makes the best video's on these topics, they are well research and presented, i have watched most of his output he's that good at it !!!
Thanks!
I was curious when NIL was in the news a while back and then kind of forgot about it. I thought this can't possibly work. Both due to the issue of alignment and the issue of keeping the mask defect free. So it turns out the first issue can be solved through looking through the transparent mask and the second issue can (maybe) be solved by just keeping the mask clean. I'm still skeptical because it sounds like an insanely difficult problem, but then I remind myself that everything in semiconductor manufacturing is insanely difficult and done against all odds.
There is no impossible only improbable
@@the_expidition427 yeah, but not even. The real killer is called economically unviable.
@@GameboygeniusIt's not economically unviable just economically not competitive. The issue is throughput but as the EUV tech becomes more and more expensive with hyper NA and quad patterning there should be a crossover point where nano imprint becomes competitive. NIL's yield issue is independent of resolution but EUV's yield becomes more problematic as you shrink the features.
Even though you can look through the template, overlay is not a problem that’s going to go away because rather than adjust the image of the mask (which can scale linearly), changing the shape of the imprint template is limited by the modulus response of the template: a decidedly non-linear process. This means when you apply a correction to say, X-mag, different areas of the template will respond completely differently. Nano imprint is cute for some niche applications but it will never be used to print anything at the bleeding edge where its resolution capabilities shine. And on top of that, it’s slower than molasses in January.
I saw the Cannon announcement somewhere and didn't understand it, thanks for explaining so deeply!
Love your description of CDs for the younglings among us! 😂
Made us feel old.
The whole "young people don't know about tapes and CDs" is weird AF.
Like, I was born at the tail of the 70s.
And I know about wax cylinders and shellac 45s.
So either young people are dumb as posts or it's all complete bullshit.
I really hope it's bullshit or it ain't looking good for the species.
It's probably bullshit.
just delivered to UT Austin just recently
Thank you for the video Jon. This video was very well put together and really helped me understand NIL in more depth.
Now I see how the Japanese semiconductor “national team” is so confident that they can catch up if not overtake TSMC at the 2nm node.
The problem is not who takes over whom. But it is the perspective of industry. TSMC does chip maker work for any fabless semiconductor design while the Japanese do for themself.
"Maybe" for the Japanese - not a certainty. You also need to get the Silicon Valley designers to buy in.
This is also a technology within the scope of chinese replication.
@@paulmichaelfreedman8334 you’re a brave man taking anything the Chinese day at face value.
@@petersouthernboy6327 It's not what the Chinese said, it's what I said! Am I wrong?
i have watched many of these video's from this maker, they are always extremely well researched and presented, keep up the good work !!!
The first time I've heard of nanoimprint lithography was about twelve years ago when Toshiba Machine developed a process for imprinting photonic crystal lattices on a GaN-on-sapphire wafer for improving the performance of blue LEDs. The process involved molding the structures into a plastic film and then using this film to imprint the structure into the resist. I believe they successfully commercialised that process.
You need to build your dad a Cantonese Spotify playlist. My mom bumps 70’s and 80’s Spanish ballads à la Julio Iglesias. Super syrupy tunes, but she’s super happy with them.
Syrupy, eh. My mom on the other hand doesn't like ballads like that and had a different liquid food related analogy to describe them. The music is so greasy that oil is dripping from the speakers.
@@Gameboygenius hell yeah! 😂
Waited for your comment on this one after seeing the news. Thanks!
So fascinating! Template replication is very reminiscent of how the production of physical music media works, with 1 master record/tape being used to create multiple clones. Hopefully this technology can find a place in the industry, even if it isn't on the leading edge.
18:25 alignment of 1nm. There Jon said that that is 10 atoms wide which is correct. Just more info, it doesn't mean about 10 atom distance inside material (eg. silicon, gold, etc). Approximately, two atoms inside nearly any materials is about 0.3nm. Means they can align within 3 atomic distance.
Imagine like chocolate chip cookies. Chocolate chips size is smaller than distance between individual chocolate chips.
Finally a video on this topic ! Been waiting for a possible episode from Asianometry after the news about this NIL machine
Got a smile out of me with the mystical description of cd
These lithographic techniques just get more and more like black magic all the time - wouldn't surprise me if they announced that there were better platter yields during the dark of the moon, or if the chanting of the heart sutra played in the background didn't give higher definition of the ICs.
your channel is hidden gem, big fan
I think nano imprint can work well with backside power delivery side of the semiconductor, it is only one or two materials copper and the insulation materials, as the purpose of this layer is solely for power delivery it is more simple and easier to work with, using EUV to this layer sounds like a match.
Secondly, since you needed to sand down the backside to expose the nTSV, the canon material sound like they can align things before printing, which is like a perfect match, if things does fall off and created a hole in the backside, if the Canon machine can find the hole and place the correct amount of filling material and applied a pure flat mask to stable the backside before building the copper at the back can improve yield.
Third, because the thing is self alignment, it also solves the possible misalignment, ie you only printed to the area you find the nm shifting if the dots from the exposed nTSV shifted 0.5nm to the left then the mask can shift left 0.5 as the machine naturally scanned what is the previous continuous print it can be just as easily to scan where these dots are and realign accordingly.
If this is the case nano imprint naturally have advantages over EUV on the backside power delivery builds.
How about Nikon's is there any next generation thingy?
Been waiting for ur take on this. It got me quite excited
This makes clear that a big advantage of photolithography is the ability to reduce the image cast by the mask: nanoimprint lithography is by definition 1:1 so there has to be some way to create features at the desired size already. Photolithography has been able to bootstrap itself down to truly tiny sizes while also being commercially viable.
Your 'definition' of a CD gave me a chuckle. :)
I'd love to see an Asianometry deep dive the exotic "compact disc" technology and canto-pop
Perhaps with the integration of chiplet designs, they can print "easy" or "smaller" chips and by stacking them like what AMD does with their chips, maybe you can "build" your chips that way.
It would be much more interesting if they managed to make the first trailing node cheap as fuck. Most people, companies and institutions don't need the very best. The second best at a fraction of the price is often a very sweet proposition.
I think they already have used machines for the cheap stuff
Actually I think this technology could work fine for magnetic disk drives. For what you said, terms like HAMR and PMR, PMR is simply how the spots are laid out on the disk surface and I don't see what this technology wouldn't work. It's just a pattern for how a SINGLE magnetic blob lays on the disk surface in relation to the other ones. PMR has a byte of spots in parallel so that as the disk is spinning under the read/write heads, instead of reading a single bit like the olden days, the heads are reading a byte at the same time (8 bits, or 8 magnetic spots). Now, the patterns have gotten more complex to increase bit density on the disk and it also means reading/writing is faster. HAMR is simply a technique involved in writing DATA to the spots, so that's not about a manufacturing process, that's about the operation of the device. In this case it's best to cover hard disk technology because this is a topic in itself.
But I don't see why the nanoimprint tech can't be used for adding the magnetic dots to the hard disk surfaces. However, disk surfaces are expected to last MANY years so it is a highly technical process.
This video has been up for 17 seconds and 64 people have opened it OMG
Bleeding edge process nodelings
Canon has a prototype metalens for photography, which was produced using this nanoimprint manufacturing system that it announced earlier this month.
This technology harkens back to the methods used to reproduce not only CDs, but also phonograph records. Can we reach further back than that? Could one pattern the resist with gravure? There would be something wonderful about creating high-technology circuits with a process once used by Dürer and Rembrandt.
I have my doubts about the production of CDs with this method, as I have "burned" CDs(CD-R) with a computer. And the CD is an optical data ... wikipedia:
"The compact disc (CD) is a digital optical disc data storage format "
Put L(ong) P(lay)/ Vinyl records for sure are printed/imprinted.
@@jarnomikkola8438 When replicated in volume, CDs are pressed, like records, as Jon describes. So, for that matter, are DVDs and Blu-Ray discs. Readable and R/W media are a completely different process.
Mass-produced CDs are printed with a stamp. A CD has little pits to denote a bit. You can also create these pits using a laser (when burning a CD-R).@@jarnomikkola8438
@@fleetingfacet True... one can do nothing in 3d, as time is a required dimention too. (+horizontal, vertical and depth)
@@fleetingfacet Time is a different dimention from width, lenght, and hight, because you have to program the printer head to actually print the different forms in a timed schedule, as they won't just appear from no-where.
I like the format of your videos.
If I was billionaire or banking firm. I'd be flying to Canon HQ and want in depth presentation on Canon NIL. If the last section of video is accurate. Anything that challenges status quo in lithography is going to be big (in end game of Moores Law).
An ex-Canon guy was just talking about this last week inside the fab and I thought, “ok if this is true, there will be an Asianometry video about it! ☝🏼”
The entertaining thing about picoliter droplets from Inkjets for JFIL is that's not even very expensive. Epson photo printers have been doing 3pl droplets for about 20 years now.
80s and 90s Canto-Pop was the golden era. Your dad has good taste 😊
I've since transferred my collection to mp3s though 😂
I like canons NIL aproach and I appreciate the competition they might bring to the marked.
This makes so much more sense than ASML's adventures into EUV and soft x-ray lithography.
Nanoimprint lithography is the future of nanofabrication.
When the mask is removed your figures show resist material remaing in the spaces between the main pattern on the surface of the substrtate. I think it would be useful for viewers not familair with processing if you accounted for the dispostion of that material, in order to accurately etch the surface of the substrate below without damage or loss of shape of the main lithographic resist pattern.
Ever since i heard about this news I've been waiting for your video
NIL sounds like it would be a perfect match for making power electronic chips which need larger process features. EUV is great for leading edge, but we need more of these trailing edge machines.
Thanks for an excellent historic view of NIL's development.
based on the process description at 7:52, i'm shocked that the process is capable of destroying less than 99% of a wafer
note: my intuition based assessments on the viability of new technologies sometimes age worse than a post exposure DUV wafer in the arizona sun
Few days ago when I read about this in the news, i was thinking Asianometry needs to do an episode on it cuz only you can explain all the complexity involved so clearly and make it understandable.
Electron beam lithography is the coolest option so we should invest in that regardless of economic considerations
10:23
Nanonex: NIL startup
nanoeX: Air-cleaning technology by Panasonic
Yes, looks like Asianometry made a typo when doing google image search. I did wonder what that startup had to do with my Panasonic heatpump
Been working on the older models but I want to learn about the new era of semiconductors!
Nice overview of a complex technology!
I appreciate being smarter after your videos. Thanks.
We need some competition in the lithography machine market. ASML is the monopoly of high-end lithography machines for cutting-edge nodes. If Canon can bring the heat and drive down prices, then we might get better pricing for finished products.
They have used this technique for making torroidal diffraction gratings for years, for making chips seems new.❤
NIL seems like the perfect choice for lower cost startup fabs and interposers in general, masks can be much larger and dust + mask durability isn't as much of an issue at 20-40nm feature sizes.
I think a video talking about masks would be a great thing. I don't think people realize just how hard it is to make a mask. For instance my understanding is TSMC takes a few days to make a mask for something like a CPU core die.
In the part of inspecting a mask I was wondering if AI could be a great help here, I think it SHOULD. Nvidia has developed the AI software to help TSMC make masks and it's supposed to reduce the time down to less than a day if I recall the article correctly. TSMC has to of course BUY the system but I think it makes economic sense to do from many days down to a day and on top of that reduce the equipment to about 1/3 in the compute side to make it. And this uses AI.
If you've made a video in the past maybe it would be good to cover what Nvidia is doing and how that can benefit companies like TSMC.
A side note, throughput on these machines isn't just about the cost of the machinery running a production line. Actually that wouldn't even be the main point. If the machines are incredibly reliable over many years, ROI comes into play. No, it's more about the cost to RUN the line, so power consumption, maintenance based on run time, etc..... If it costs a company very little to run a line production can be slower and this should make sense. However a company has commitments so they have to meet a throughput that allows them to be profitable and meet their customer's needs.
Reliability is insignificant because of plan obsolescence. It does not matter if the tool last for 30 years when the shelf life of the technology is only 5 years. Yes you can fab 5nm process until 2033 that does not help you when the industry has already move on to 0.8nm.
@@kazedcat No that's not true. First you mean 1.8 because the node path is 3nm which TSMC is on right now, then 2nm, then 1.8, then 1.7, etc..... MAYBE by 2033 fabs are at 1.7, probably 1.8 because it's getting harder to move to each progressively smaller node. But nodes are just a name. TSMC's N3 isn't at the density they said they would be at so even with the fake naming scheme the lead company isn't making its goals, so it's N3 is really about what N4 should have been. Really. Go read. High-NA EUV is supposed to help get them back on the path of smaller nodes, as in REALLY SMALLER nodes, not just in name only. The companies have to get good at using the new lithography though and that takes about a year.
But next is an assumption that the leading node is where all the business is and that's PURE fallacy. The fabs get a good 5 years out of the leading edge, and that means heavy business by companies making high end compute products, or Apple.
What's going to happen is the nodes in the realm of 20 - 5 will start to replace most of the older nodes and that's because costs for materials are going back up, Something that may have been on nodes like 28 and larger will fade away and these newer nodes will replace them. You do hit a point where shrinking analog circuits isn't so great but you still get scaling down to about 6nm.
But we're heading for a technology war between China, Russia, N Korea, Iran and a few other insignificant countries and the free world, or mostly free world, and materials used to make ICs INCLUDING silica, which becomes silicon are going to go up in price as China decides to greatly reduce what it sells, and they control the market of many of these materials including silica, which means even making those large crystals are going to get more expensive. So they'll be much more pressure on cutting the use of materials which will close a lot of those older fabs which means ever smaller nodes will become general purpose nodes.
You know when AMD started using TSMC N7? 2019. Do you know AMD is STILL making products with N7? So even with just AMD alone TSMC is 5 years on a node that they started producing products with in 2016. Maybe what you don't realize is companies like AMD, Intel and Nvidia make a new generation of products over about 1.5 - 2 years as a NEW generation. But if that generation is successful they'll keep making that product. AMD will keep making Zen 3 and RDNA 2 graphics (6000 series) into 2024). They've continued to make those products as low cost products vs. their new line of Zen 4 and RDNA 3 graphics. Zen 2 was the first gen AMD CPUs to use TSMC N7.
So here it is coming up on 2024, TSMC has been making products on an N7 process node since 2016 and they're STILL pumping out lot of products for different companies on that node.
This stuff stays in production at a very profitable rate for the fabs for more years than you think, even making high end compute products.
@@johndoh5182 You don't know how to count you shrink around 30% per generation. So 3nm then 2nm then 1.8nm then 1.2nm and 0.8nm assuming the rate of 2 years per full node shrink will continue then at 2033 we will be at 0.6nm. I am accounting a slow down so 0.8nm in 2033 is a good prediction.
@@kazedcat Hey thanks for the insult shit head. I was polite with my comment, this will be my last and we'll agree to disagree.
Roadmaps for process nodes have changes so many times it's ridiculous. At one time Intel showed a process map going from 20A to 14A. Yeah they changed that a couple years ago and in 2023, and it's hard to find and same is true with TSMC, finding a projected roadmap for more than about 2 steps, Intel shows 20A, then 18A, then 17A. Now, considering both TSMC and Intel are both WAY behind their roadmaps they published around 2019, 2020, I'm going to stick with what I said. There has ALREADY been a big slowdown. Intel was supposed to be on Intel 4 a couple years ago, and right now all they can do for NEXT year is put out laptop parts on it. Same thing happened to them moving to their node formerly know as 10nm, now called Intel 7. It's going to be 2025 when Intel has desktop parts out on Intel 4. That's FOUR years going from Intel 7 to Intel 4.
It's POSSIBLE Intel may try to skip Intel 3, or they may still try to develop Intel 3 but maybe using High-NA to get to Intel 3 BEFORE they move to Intel 20A. But they have clearly published THIS year that their steps after 20A is 18A and then 17A. Then next projected step would be Intel 14A, but they're not publishing this in formal roadmaps that they release to their board of directors. They dropped everything below 18A.
If you think these companies will magically get to something below 1 by 2033, fine with me. It's not happening but sure thing bud. And no there is no MAGICAL percentage that nodes shrink each gen. There is something that Intel, Samsung and Intel WANT to do, but that doesn't mean they have, and TSMC N3 is a perfect example of that. Once again YOU do the reading. Don't read anything older than 2023 though because that's what you did to come up with the numbers YOU did.
This is from THIS year:
"Anyway, the bottom line here is that some critical elements of TSMC's N3 and Intel's 4 nodes are looking very, very similar. Both TSMC's and Intel's high performance logic cells clock in around 125 million transistors per square millimeter.
There are other chip elements from both manufacturers that will exceed that density. TSMC's N3 node will extend all the way to 215 million transistors per square millimeter. "
This means at BEST TSMC is about 25% vs. N5. But of course here you have to understand that a process node comes with different libraries, with one being a typical low density library and another being a high density library.
So here is the real truth. In use cases such as hi performance computing where clock speeds are as fast as possible, neither TSMC or Intel low density libraries have kept that pace. Also, Apple is frustrated right now with TSMC N3 because it's not meeting its production demand because the defect rate has been high. So once again, the rate at which these new nodes are coming is longer. AMD was supposed to have RDNA 4 and Zen 5, both coming out next year, on TSMC N3. That's been pushed back to some products on N4 and other products on N3.
Considering NO company can really start work yet on a 2nm process UNTIL they have ASML High-NA equipment, I don't expect to see 2nm (once again a meaningless term) until 2026 because it takes a LONG TIME to develop these nodes. Intel is supposed to get a first delivery at the end of this year. They SAY they'll have 20A by 2025. Considering they're about 1.5 - 2 years late on their nodes for the last 3 nodes including the unreleased Intel 4, I'll make the call now, 2026 or 2027.
TSMC will get High-NA in 2024. They've been better at getting nodes out but they've still struggled with both N5 and N3 both being behind, I'll say 2025 they MIGHT have their first run with Apple, who is always first on a new node once it's good enough for production.
But really, that's what you want to talk about when you're first point was how many years a new node will have GOOD rates of production on it??? And you're wrong there too?
And I didn't even give a complete picture on a new node. First run will be with risk partners. APPLE falls into that category. That's about 1 to 1.5 years depending on different factors. Then the NEXT group of chipmakers gets on that node. That doesn't mean Apple is no longer on that node though. AMD is NEVER on a first run for TSMC because they make critical components not just for consumers but also enterprise, so they are on the NEXT run. They could have 1 or 2 generations of products on that node. So this is high end computing, on a node that came out and was already in production before a company like AMD trusts it enough to use. Following the customers like AMD are OTHER customers that make components for computing. So you basically have THREE waves of chipmakers progressing through a node, and if a company like TSMC has a delay, those 3 waves can be many years. But once again, most companies don't just DROP product lines after a single run. They could be producing a line of products for 3 - 4 years. So yes, a single node or generation of nodes since there are variants of the same node can have solid production for about a decade.
Over, OUT.
@@kazedcat you seem to be pretty misinformed about how semiconductor nodes are used. Right now, hardly any of a wafer uses leading edge nodes. Most of the semiconductor is still produced using older techniques. This has to do with yields and cost efficiencies. There are certain parts of a finished product that are best made using cutting edge tech, but the majority of it is produced using a gen or two older tech. I work in a leading edge semiconductor fab and we still have plenty of litho tools that are 10+ years old.
Also, process node names/sizes are mostly meaningless nowadays. You're using those terms like that relate to physical transistor size, which they don't, and has been repeated on this channel dozens of times. You're quoting numbers that don't really have any meaning. Johndoh explained this to you pretty well and you seem to have ignored his explanation.
So just to recap, you don't make a semiconductor out of one process node. You use a variety of nodes to produce a single product. The majority of those nodes are not leading edge. This is especially true with new chiplet designed products.
Was waiting for this. Didn't disappoint.
I WAS WAITING FOR THIS VIDEO!!! EEEEEEEEE
Nice to hear about some alternatives to EUV. Good to have a plan B.
Carbon assembly using X-rays. Can hit resolutions down to 1nm, and thus can build essentially indestructible masks, or as close to it as possible as the structure is cubic in form, which is the strong arrangement of carbon known as diamonds.
Currently only De Beers owns a lab doing this, as far as I know. The process is still unrefined and messy, but I am certain that it can build masks for this process.
NIL for rapid production of the higher metalic layers, with traditional processes for the transistor fabrication? - feels like physical lithography would be better for larger features..
why dont they lubricate the inside of the template to avoid shearing defects while pulling the template off?
This NIL reminds me that Lithography for an optical technology is actually a misnomer. Lithography means drawing with stone, the origin of steppers is put a pattern on a stone and then stamping or transferring this pattern to the will be chip. As such this NIL seems more like the historic way to produce chips.
I still use the vinyl aka the "black" frisbee to listen to my static Spotify playlist, because the "silver" ones are a little too advanced for me 😅😅
If you can make the machine 10 times cheaper than an EUV machine, then you don't need equal throughput, individually. Just have more machines. Cool, I haven't keep up with the developments on this since 2006.
NIL might be good for smaller chips or maybe FPGA.
Ah, you mention memory chips at the end.
This doesn't scale perfectly in practice as fab real-estate is a recurring issue. Not that EUV don't have them, especially on the non-cleanroom floors of the fab.
I hope you can talk more about FLASH memory and history/projections for SD card size.
Any updates after a year?
I bet you if those defects would have been named by biologists, we here wouldn’t even be able to pronounce them
The original machine had a base-plate of prefabulated aluminite, surmounted by a malleable logarithmic casing in such a way that the two main spurving bearings were in a direct line with the pentametric fan.
Please do video on Novellus / Lam research
OMG nothing has made me feel older than your explanation of what a CD was 😂
Is there finally some kind of safeguard against side fumbling?
The nanoex logo used is the commercial trademark by Panasonic and not the semiconductor nanoex though. Nice video btw
Creating the mask on Nanoimprint lithography, in the most important process of improving producing wavers on EUV Lithography.
To big to develop yourself, the mask quality was the biggest problem, joying ASML was a smart move.
Always interesting content, thank you.
This process feels very similar to injection molding but at a very small level. Not small as in production scale but small in what product is produced
This is why use I use youtube. Your videos are gem❤
I would enjoy seeing the history of HP. I really enjoy your videos.
I was exactly looking for this
passive aggressive emails from metrology sounds hilarious lol
I assume that the equivalent of a resin printer that uses a higher resolution display as the equivalent of the template isn’t. But one wonders if further developments of high resolution displays couldn’t eventually replace some of of these technologies, maybe not at the smallest size, but very small sizes?
8:04 middle-out
Im considering... But Im not sure yet.
for my colleagues, I think ASML's notice is 2 months btw
I can't help but think that at some point the cost of the soup-like homogenate err... resist... becomes uneconomical even at scale...
Why not replicate enough templates to allow for an entire wafer to be produced in parallel all at once? That would be a major multiplier in terms of speed and hopefully reduce costs/prices.
Mask inspection, and if you're talking about machines working in parallel it becomes an issue of clean-room space.