Even in steady state the output is driven to High by VDD using PMOS, and Output is driven to LOW by ground using NMOS. Then in sleep mode both NMOS and PMOS are off, how will the output be continuosly driven to low or high states in steady state? Or maybe there is no discharge path/charge path in sleep mode and output stays high/low.
We use sleep = 0 in transient state when we have to change the input, in steady state , sleep = 1, As there is no current through CMOS in steady state, so only off state current will flow through both sleep transistors
I think at 10:20, V_th of N_1 should be greater than N_0. ( Sir is saying lesser than N_0.)
Yah you are correct.
he is saying the same in the prev lecture also :)
Thanks for the content!
Ajit Agarkar of Electronics field 🌚🔥
He talks like Rahul Gandhi though!
Even in steady state the output is driven to High by VDD using PMOS, and Output is driven to LOW by ground using NMOS. Then in sleep mode both NMOS and PMOS are off, how will the output be continuosly driven to low or high states in steady state?
Or maybe there is no discharge path/charge path in sleep mode and output stays high/low.
your last line is the answer. I had the same doubt, but it made me understand, tysm
We use sleep = 0 in transient state when we have to change the input, in steady state , sleep = 1, As there is no current through CMOS in steady state, so only off state current will flow through both sleep transistors
what a explanation
if dibl is dominating how is vth of n1 increasing shouldn't it be reducing then???
same question , did you get any solution?
I guess , he was mistaken earlier. He should have told that Vth of N1 is greater than No due to DIBL
Vgs will be decreased as source having Vx, then Vgs-Vtx need to be more to cross the Vth..
If I am wrong please make me correct...