I think some transistor capacitance videos are missing i am not understanding the vdd/2 concept ,and equivalent rc model and when did module 3 came from jumping from module1
I am totally confused in here ? Partially understanding everything when the concept of vdd/2 for delay purposes taught and when was equivalent rc model taught i did not came accross something like that plzzz upload the videos if anything is missed
The way he explained that NMOS should be used in PDN and PMOS should be used in PUN was commendable.
Anyone struggling to find the VDD/2 concept can refer the Inverter 12 - Nmos Transistor ON resistance and Inverter 13 - Elmore delay lectures
When pmos discharging why vgs=-vc(t) didn’t get plz explain
When did we come across the concept - discharge from Vdd to Vdd/2 for delay purposes? Also, in which lecture equivalent RC model was discussed?
Yea, sir please always upload all the content.
Yeah i agree I am totally confused in here ? Partially understanding everything
@@adeddy8138 ua-cam.com/video/j9kMj0Yr6_Y/v-deo.html
This is the missing lecture, the first 27 minutes
I think some transistor capacitance videos are missing i am not understanding the vdd/2 concept ,and equivalent rc model and when did module 3 came from jumping from module1
I am totally confused in here ? Partially understanding everything when the concept of vdd/2 for delay purposes taught and when was equivalent rc model taught i did not came accross something like that plzzz upload the videos if anything is missed
have u got this videos or not ?
Why do we think in terms of NAND-NOR logic in CMOS?
Because they are good at switching time and power consumptions and their logic efforts are less
i did not understand the expression for charging ..please someone could you explain...
understand hopefully
@@ajiths1689did you understand?
Sir why is Vdd negative for PMOS charging?
Revisit device physics. In pmos, channel is formed when gate voltage is lower than threshold voltage.
Yes
@@akashekhar and why it is not vgs(t)=vdd-vc(t)