Capacitive coupling in Dynamic CMOS Logic

[@ASPIRANT-hw1qe]

Sir thankyou for the this video

[@InderjitSingh87]

Most welcome

[@rockingstone7700]

perfect explanation sir

[@InderjitSingh87]

Thanks and welcome

[@InderjitSingh87]

Note: @3.35 seconds in video, there is a correction, CLK is 0 instead of 1, then Mp transistor is ON, and pull down network is OFF, Mn transistor is OFF, so Vout1 level is close to VDD

[@digambarbhole9467]

@ 3.35 if our CLK is 1 then how the pull-down network would be off, in fact, pull up a network should be off
please clarify

[@InderjitSingh87]

Note: @3.35 seconds in video, there is a correction, CLK is 0 instead of 1, then Mp transistor is ON, and pull down network is OFF, Mn transistor is OFF, so Vout1 level is close to VDD

[@digambarbhole9467]

@@InderjitSingh87 thank you sir

[@kanishr5360]

Sir can you send these notes

[@InderjitSingh87]

Kanish, I always encourage learners to note down important concepts from the video. That will be your notes.

[@InderjitSingh87]

Note: @3.35 seconds in video, there is a correction, CLK is 0 instead of 1, then Mp transistor is ON, and pull down network is OFF, Mn transistor is OFF, so Vout1 level is close to VDD

[@nupurdewangan7176]

sir plz send this notes

[@InderjitSingh87]

Nupur, I always encourage learners to note down important concepts from the video. That will be your notes.

[@InderjitSingh87]

Note: @3.35 seconds in video, there is a correction, CLK is 0 instead of 1, then Mp transistor is ON, and pull down network is OFF, Mn transistor is OFF, so Vout1 level is close to VDD