Can we choose another Eular Path, As for example ADECB? Is there any specific trick to find a specific Eular path from a schematic diagram? I noticed your metal cantact aren't being overlapped but according to my Euler Path(ADECB) the contact are being overlapped...
Thankyou for your valuable comment. You can take any path: 1.That should traverses through all the nodes. 2. Euler's path must be same for both PUN and PDN.
mam , how did you take eulers path in pull down network as CBADE , shouldn't it be CADEB or BADEC , cause connection to C and B is kind of interupted right ? i could be wrong though.
@@ExploretheWAY Okay but can you explain me why there is difference in pMOS and nMOS terminals? In pMOS you labeled Source, Gate and Drain and in nMOS you labeled Drain, Gate and Source?
@@aashishgoreja7455 The source of a pMOS is connected to VDD whereas the source of a nMOS is connected to GND. The drain is the path that leads to the output Y. This is why the gates were labeled this way.
Bahut shukriya, you gave me the confidence I need for the final exams
Most clear explanation on this!
Ma'am, 4:42 you mispelled : drain of A and C are connected together, not D
true
yes
really great video and perfect explanation thank u
Can we choose another Eular Path,
As for example ADECB?
Is there any specific trick to find a specific Eular path from a schematic diagram?
I noticed your metal cantact aren't being overlapped but according to my Euler Path(ADECB) the contact are being overlapped...
Thankyou for your valuable comment.
You can take any path: 1.That should traverses through all the nodes. 2. Euler's path must be same for both PUN and PDN.
@@ExploretheWAY Thanks for your answer
Hat's off,mam🔥
This helped so much! Thank you!
mam , how did you take eulers path in pull down network as CBADE , shouldn't it be CADEB or BADEC , cause connection to C and B is kind of interupted right ? i could be wrong though.
The Eular's path should be the same for both Pull Up and Pull Down networks.....
No it is not interrupted, as you can see it follows a perfect path through the circuit
Very good explanation
Superb content
very helpful!thank you so much
Thank you.. You helped me a lot..
Is that important eular path
Garda ura dia
so nice!!!!!! love you!!!!
Mam substrate contact means,
I think this schematic has an issue..Don't we have a series connection between A(B+C) and D.E? It looks parallel to me. Nice video though
There is a parallel connection between A(B+C) and D.E in the pull down network. This schematic is absolutely correct.
excellent mam:)
How to take directions for Euler's path
same doubt please clear
you can start at any node, but it traverses through all the nodes and the path must be same for both PUN and PDN.
For pmos anticlockwise and for nmos clockwise
@@PSEC_Abhi Are you sure bro?
What is substrate path?
Nice
❤️❤️❤️
I think you made a mistake in labeling the gates in pMOS. Its Drain, Gate, and Source but you labeled Source, Gate, and Drain.
No mistakes. Everything is correct.
@@ExploretheWAY Okay but can you explain me why there is difference in pMOS and nMOS terminals? In pMOS you labeled Source, Gate and Drain and in nMOS you labeled Drain, Gate and Source?
@@aashishgoreja7455 The source of a pMOS is connected to VDD whereas the source of a nMOS is connected to GND. The drain is the path that leads to the output Y. This is why the gates were labeled this way.
@@aashishgoreja7455 first learn thoery about pmos and nmos transistor then point out mistakes :)
@@aditya9573you tell them. People go in the comments and everything is a mistake to them while they don't even know the theory :>)
😍Thankyou🙏
There can be multiple paths why did u choose starting from C only??
yes, there can be multiple paths. You can choose one. But that must be same for PUN and PDN.
@@ExploretheWAY PUN PDN? stand for?
PUN stands for Pull Up Network and PDN stands for Pull Down Network.
@@ExploretheWAYy u take C only
@@illakiya2023 you can start from anywhere. Make sure the path is same for PUN, PDN
why you did not give connections to the source?
All the sources are properly connected.
😘😘😘
Most probably number of interruption have to minimum for a loop...
i think in C n diff it will be S-D instead of D-S
Thank you
Thanks..
Thank u
Thanks
Thanks
thank you