I loved the video, could you upload a video where a typical exam is solved? For example: Given the layout of the figure, it is requested: a) Bar diagram. b) Diagram with transistor symbols. c) Circuit operation table indicating, for all possible combinations of its inputs, the state of the transistors, conducting network and its equivalent resistance, logic value at the exit. Indicate the expression of the logical function performed by the circuit. d) Assuming that a capacitance of 0.01pF is connected to the output, find the maximum delay produced by the gate and for what type of transition it occurs. Data: Rp = 3kΩ, Rn = 1kΩ.? ......
left? All the transistors in the upside are PMOS and all transistors in the downside are NMOS because the circuit was building using a complementary logic with Pull Up (PMOS transistors) and Pull Down (NMOS transistors).
correct me if im wrong sir. from the pmos logic you found, you just can do the opposite for the nmos. is it applicable for all circuit if we only just opposite the pmos to get the nmos? thanks in advance sir.
Thank you Sir! Please upload more on complex layouts.
Thanks❤You help us.
Explained very clearly, thank you
I loved the video, could you upload a video where a typical exam is solved?
For example:
Given the layout of the figure, it is requested:
a) Bar diagram.
b) Diagram with transistor symbols.
c) Circuit operation table indicating, for all possible combinations of its
inputs, the state of the transistors, conducting network and its equivalent resistance, logic value
at the exit. Indicate the expression of the logical function performed by the circuit.
d) Assuming that a capacitance of 0.01pF is connected to the output, find the maximum delay
produced by the gate and for what type of transition it occurs. Data: Rp = 3kΩ, Rn = 1kΩ.?
......
Thank you so much for this video!
It helps me a lot!
thanks for the clear and concise video!
Thanks a lot sir
nice explanation and like your voice too :)
Can you make this kind of video?
Your videos are really great.
Thank you, this was helpful.
Thank you so much
How do you know the transistors on the left are PMOS?
left? All the transistors in the upside are PMOS and all transistors in the downside are NMOS because the circuit was building using a complementary logic with Pull Up (PMOS transistors) and Pull Down (NMOS transistors).
PMOS body needs to be connected to VDD in order to be properly biased so it makes sense to be on the top
Thank u sir, but can you help me in solving such circuit
adamın hasısın.
thank you
correct me if im wrong sir. from the pmos logic you found, you just can do the opposite for the nmos. is it applicable for all circuit if we only just opposite the pmos to get the nmos? thanks in advance sir.
no, you cannot assume such thing unfortunately
Bless on milk of you mother
So unhelpful