Very well explained sir, thank you. I've a doubt, we haven't yet given the clock so how max trans, Max cap violations be observed ? And how does the tool fix those in intial_drc
Hi sir I have a question please. For some reason I get very bad global routing congestion after place-opt when using scan shift mode, but it is Ok when I use only functional mode. Do you have an idea what might be causing this? Many thanks for your videos !
The aim of synthesizer tool is to synthesize the logic to a particular technology and optimize the logic. Now a days tool is so much advanced that with physical synthesis it does buffering of high fanout nets too
@@VLSIAcademyhub people have asked doubts in comment sections and you have replied them(1 year back comments ).but now your comments are is not visible
Very well explained sir, thank you. I've a doubt, we haven't yet given the clock so how max trans, Max cap violations be observed ? And how does the tool fix those in intial_drc
Okay, thank you
Hi sir I have a question please. For some reason I get very bad global routing congestion after place-opt when using scan shift mode, but it is Ok when I use only functional mode. Do you have an idea what might be causing this? Many thanks for your videos !
Why syntheisiser dont put HFN buffer in synthesis stage ?.. This is known to synthesisier .
The aim of synthesizer tool is to synthesize the logic to a particular technology and optimize the logic. Now a days tool is so much advanced that with physical synthesis it does buffering of high fanout nets too
why previous comments of yours are not available in comment session sir ?
Didn't get your question... Which comments are not visible?
@@VLSIAcademyhub people have asked doubts in comment sections and you have replied them(1 year back comments ).but now your comments are is not visible
Tqqq sooo much sir