This video would be easier to understand if metric units were used! I'm in the US too, but most manufacturers and our entire design process has switched over to metric Hope this helps and great videos Altium team!
I hear different recommendations about when to use SMD vs NSMD pads. My vague feeing is, use NSMD pads, until things get small, then use SMD pads. But how small is small, and what are the actual problems with using SMD pads everywhere?
One thing you can do with SMD pads is you can still hit a Class 2 or 3 recommendation for a pad size with small pitch while still being within the exposed solderable area definition in IPC standards. I've had fabricators recommend this specifically for Class 2 and with laser-drilled microvias when pitches get really small.
Another important rabbit hole for via-in-pad is BGA collapsable vs non-collapsable balls. Bigger pitch BGAs have balls that collapse onto the pad, so there’s a risk of the ball itself getting sucked up into the vía through capillarity if you haven’t filled it. Smaller pitch BGAs (generally) have balls that don’t collapse, making this issue less likely.
@Jerome Demers Basically it could pull solder to the back side of the board, where it could possibly solidify and create a short. It could also leave insufficient solder between the pad and the component, making a weak connection that might fail under thermal cycling or mechanical shock.
Hi Dr. Peterson. I need to design "via in pad" now. But I have noticed that Altium 22's "Via Types & Features" panel does not have any options for "via in pad". So, would you please confirm if Altium 22 cannot do a "via in pad" design？ If yes, then, how do you do it? Thank you!
Can you please explain how to make design rules specific to via-in-pad, for example minimum annular ring, hole size etc. There seems to be no query that ever applies to vias of this type
On the back side of the BGA with through-holes yes definitely. That's actually a good point too because you would have to do it even with dogbone fanout. I've shown an examples of this in another video on BGAs.
In your first example, couldn't you just tent the bottom of the via instead of doing a fill + cap? While reflow could result in solder flowing into the via, it would not exit the bottom to impact secondary side components. Perhaps this would complicate the paste volume needed on the top side though.
Yes you can tent just that via, but you would still need to make sure there is enough exposed pad area so that there is a sufficiently large solder fillet. If you can manage to place the via so that there is enough solderable area then the simple option is to just tent. Otherwise fill + cap is preferred.
Very nice video of Via in Pad. Question: Once I flubbed a job interview for high speed clock PCB design, the guy wanted to know how to layout a part where two different clocks were in adjacent pins. I'm guessing that you do via-in-pad down to different layers, separated by a ground plane. Is this the way, or am I way off?
Yes that's one way to do it, assuming you don't have any control over the pinout/pin selection (like in an FPGA). You could also go down to the same layer and route them in orthogonal directions. Also if the pitch is large enough then you might not need via in pad.
How do I choose a via size for the exposed pad of an IC? usually there is a suggestion for that in the datasheet somewhere.. but for AD9578 I can't find anything in the datasheet?
You can choose this based on the size of the pad, the pad should generally be larger than the via hole and pad size to ensure there will still be a place to solder, and it helps ensure you don't create an artificially enlarged pad when applying the via-in-pad placement.
The IPC-7351 standard has a table that provides ball size and pad size data for use in creating BGA footprints. I added the blog link in the description.
How does IPC class 3 looks on VIP? I thing there is huge impact on reliablity, but did class 3 accept VIP or other words did any pcbhouse can make PCB in class 3 with VIP?
IPC Class 3 vias with VIP should be filled with a non-conductive epoxy, capped, and then plated over with 12 micron thick copper. There also needs to be planarity maintained, so there cannot be much protrusion, I think less than 50 microns is the requirement. There is also a clearance requirement for these features, pad edges have to be at least 6 mils from other copper features. This will definitely keep you compliant with hole wall-to-hole wall limits with your fabricator, but it can make dense through-hole boards pretty difficult. The minimum allowed drill size is 6 mil, so the standard allows for the entire range of possible mechanical drilling options.
So where is the Altium instruction for using these different types of IPC 4761 that Altium lists in the Via Properties Panel? Seems like there's no way to use these during interactive routing. Altium seems to have a problem with not fully implementing a new feature. We really need to be able to declare various capped IPC 4761 vias in the rules, then be able start routing at a Pad, hit the numeric + key, and be able to toggle thru the various vias INCLUDING the capped vias. Ideally, Altium should be able to discern when a user changes layers on the pad, to allow selection of various IPC 4761 vias.
I agree it would be nice to be able to set it in the rules, then you could have it set based on whether it's in a Room. Right now you can create a rule for tenting using the Solder Mask Expansion rule, just do it by Room and set it to tented. It would be great to have the other options in the Rules and Constraints editor though.
@@Zachariah-PetersonHi Zach. If I specify a via as say a Type 7 (or how ever I want to designate a VIP), how do I output only the VIP vias as a Gerber plot (which should also show up in ODB++) for the PCB fabrication?
This video would be easier to understand if metric units were used! I'm in the US too, but most manufacturers and our entire design process has switched over to metric
Hope this helps and great videos Altium team!
buffest engineer on the internet
👀👀👀
I hear different recommendations about when to use SMD vs NSMD pads. My vague feeing is, use NSMD pads, until things get small, then use SMD pads. But how small is small, and what are the actual problems with using SMD pads everywhere?
One thing you can do with SMD pads is you can still hit a Class 2 or 3 recommendation for a pad size with small pitch while still being within the exposed solderable area definition in IPC standards. I've had fabricators recommend this specifically for Class 2 and with laser-drilled microvias when pitches get really small.
Another important rabbit hole for via-in-pad is BGA collapsable vs non-collapsable balls.
Bigger pitch BGAs have balls that collapse onto the pad, so there’s a risk of the ball itself getting sucked up into the vía through capillarity if you haven’t filled it. Smaller pitch BGAs (generally) have balls that don’t collapse, making this issue less likely.
so if it suck inside the via, this could lead to bad connection? or work but eventually fail under thermal events?
If you're doing via in pad though, you would want to fill the vias anyways to prevent capillary action.
@Jerome Demers Basically it could pull solder to the back side of the board, where it could possibly solidify and create a short. It could also leave insufficient solder between the pad and the component, making a weak connection that might fail under thermal cycling or mechanical shock.
Hi Dr. Peterson. I need to design "via in pad" now. But I have noticed that Altium 22's "Via Types & Features" panel does not have any options for "via in pad". So, would you please confirm if Altium 22 cannot do a "via in pad" design？ If yes, then, how do you do it? Thank you!
Im sure you figured this out by now, but Altium 22 does do VIP. You just put the via in your pad, theres no specific settings for it.
Can you please explain how to make design rules specific to via-in-pad, for example minimum annular ring, hole size etc. There seems to be no query that ever applies to vias of this type
We're filming a video about your question today
I love the BGA Inventory showing -100% lol
Explained very well
With 0.8mm pitch BGA its more likely to use via in 0402 pad to keep the bypass caps close to the appropriate BGA pad.
On the back side of the BGA with through-holes yes definitely. That's actually a good point too because you would have to do it even with dogbone fanout. I've shown an examples of this in another video on BGAs.
In your first example, couldn't you just tent the bottom of the via instead of doing a fill + cap? While reflow could result in solder flowing into the via, it would not exit the bottom to impact secondary side components. Perhaps this would complicate the paste volume needed on the top side though.
Yes you can tent just that via, but you would still need to make sure there is enough exposed pad area so that there is a sufficiently large solder fillet. If you can manage to place the via so that there is enough solderable area then the simple option is to just tent. Otherwise fill + cap is preferred.
Can via in pad, still be chosen over dog bone layout for higher pitch ... considering signal integrity?
Yes it can
Very nice video of Via in Pad. Question: Once I flubbed a job interview for high speed clock PCB design, the guy wanted to know how to layout a part where two different clocks were in adjacent pins. I'm guessing that you do via-in-pad down to different layers, separated by a ground plane. Is this the way, or am I way off?
Yes that's one way to do it, assuming you don't have any control over the pinout/pin selection (like in an FPGA). You could also go down to the same layer and route them in orthogonal directions. Also if the pitch is large enough then you might not need via in pad.
How do I choose a via size for the exposed pad of an IC? usually there is a suggestion for that in the datasheet somewhere.. but for AD9578 I can't find anything in the datasheet?
You can choose this based on the size of the pad, the pad should generally be larger than the via hole and pad size to ensure there will still be a place to solder, and it helps ensure you don't create an artificially enlarged pad when applying the via-in-pad placement.
How did you determine to use a .3mm land when the ball size is .4mm?
The IPC-7351 standard has a table that provides ball size and pad size data for use in creating BGA footprints. I added the blog link in the description.
How does IPC class 3 looks on VIP? I thing there is huge impact on reliablity, but did class 3 accept VIP or other words did any pcbhouse can make PCB in class 3 with VIP?
IPC Class 3 vias with VIP should be filled with a non-conductive epoxy, capped, and then plated over with 12 micron thick copper. There also needs to be planarity maintained, so there cannot be much protrusion, I think less than 50 microns is the requirement. There is also a clearance requirement for these features, pad edges have to be at least 6 mils from other copper features. This will definitely keep you compliant with hole wall-to-hole wall limits with your fabricator, but it can make dense through-hole boards pretty difficult. The minimum allowed drill size is 6 mil, so the standard allows for the entire range of possible mechanical drilling options.
I'll do a video on it.
Thank you so much Zach. Good video.
So where is the Altium instruction for using these different types of IPC 4761 that Altium lists in the Via Properties Panel? Seems like there's no way to use these during interactive routing. Altium seems to have a problem with not fully implementing a new feature. We really need to be able to declare various capped IPC 4761 vias in the rules, then be able start routing at a Pad, hit the numeric + key, and be able to toggle thru the various vias INCLUDING the capped vias. Ideally, Altium should be able to discern when a user changes layers on the pad, to allow selection of various IPC 4761 vias.
I agree it would be nice to be able to set it in the rules, then you could have it set based on whether it's in a Room. Right now you can create a rule for tenting using the Solder Mask Expansion rule, just do it by Room and set it to tented. It would be great to have the other options in the Rules and Constraints editor though.
I almost forgot, the other thing you can do is to use the pad/via template features, from there you can assign IPC 4761 types to via objects.
@@Zachariah-PetersonHi Zach. If I specify a via as say a Type 7 (or how ever I want to designate a VIP), how do I output only the VIP vias as a Gerber plot (which should also show up in ODB++) for the PCB fabrication?
Ah! When I update the vias I have in VIP, with Type 7, now the capping and filling layers show up in Gerber outputs! So, I guess I figured this out...
But...some footprints have vias already pre-built into the footprint. I don't see an option to specify via type for these vias. Any help on that?