It's been nearly 2 years I'm working on my free time on a TFT dashboard for an old motorcycle, and I have a lot of troubles dealing with EMI. This video is really helpful understanding how that works and how possibly solve it. Thanks for all these information 🙏
One of the benefits I hear for using copper pour is to reduce the amount of etching chemicals used during manufacture. My understanding is that the copper layer is applied as a foil sheet to the full board surface and then etched away. Obviously it's important that the copper pour can't significantly affect signal integrity so it's really only applicable to slow-speed circuits?
Copper pour does matter at intermediate layer thicknesses where the parasitic capacitance to the pour is comparable to the capacitance to ground. That part of it matters more for high-speed circuits that are not on really thin layers, and the distance from the pour to the trace that you can tolerate depends on the impedance deviation you can accept. To solve that, just design the trace as if you were always going to use the pour anyways and then use thinner dielectric in the signal layers. For the etching part of it, you would have to get specific cost differences from a manufacturer. It is true that less of the etchant is needed when pour is included, but this could be insignificant to the overall cost when you get to high volume. Also, I have never had one of my manufacturers tell me that I can reduce cost if I just included the copper pour!
5:55 it absolutely true, "If copper pour is not necessary, why do all the PCBs I see use copper pour on both the top and bottom? I don't understand at all. Even in your reviews."
At the time of doing this video I had not done a lot of instruction on the difference between 2 layer and 4 layer PCBs, but the distinction is relevant here. In a 2 layer PCB, copper pour is sometimes the only way to provide enough ground to provide return currents for digital signals, especially if you have double sided placement. If you see the copper pour in an assembled PCB, it might just be a 2 layer PCB. Once the component placement and routing density get high enough, it is not enough to apply ground with copper pour, so the easiest strategy is to use 4 layers with internal ground planes. In that instance, the copper pour is probably not needed as long as the outer layer is thin enough. These other issues with coupling across a region of copper pour is similar to what you would see with guard traces, the difference is that a copper pour region is just a wide guard trace.
I don't know, Zach, but I found that thumbnail to this video hilarious... Hat's off to the person who made it... You like some kind of Tribal Chief 😄 As always learning a lot from these videos. Thank You.
I recommend that the wavelength calculation should be corrected for effective dielectric constant of the medium of propagation: air + dielectric in the case of Microstrip or GCPW, or dielectric for Stripline. In the above example, 3GHz wavelength in FR4 would be closer to 40mm then the 100mm calculated assuming vacuum dielectric.
As far as the use of Dk-eff for wavelengths and stitching via spacing determination, that calculation would only be valid in the vicinity of the trace (when the trace is on the surface layer) where the transmission line appears coplanar. However, waves traveling into the dielectric or originating in the dielectric would only consider the value of the dielectric. The other thing to think about here is the fact that the wavelength will be longer when Dk-eff is used compared to just Dk because Dk-eff < Dk. So as a result, if you size the stitching based on Dk, it will also provide the same shielding effectiveness in the region around a microstrip. The wavelength difference is only about 20% to 30%.
Awesome!! Very nice and clear explanation about the via stitching and gnd copper pour everywhere. And yeah, almost everything in PCB Design comes down to proper stack-up and traces spacing.
The effectiveness for stripline and microstrip varies, we are essentially creating a large guard trace when doing this. In general for microstrip, getting an effective reduction requires to tie the copper to ground at each end of the interconnect, which is why you will see the stitching vias used as it will ensure this. For the stripline case you can watch this video to see the level of change by looking at near-end and far-end crosstalk: ua-cam.com/video/K1ob42Pv74Y/v-deo.html
I want to add one point from a assembly and production point of view. Not so much from the electric side. Having multiple layers, including the TOP and BOT with evenly distributed copper layers on it can be kinda helpful to counter PCB warping, specially on bigger layouts. Of course this does not help at all if the signal integrity is compromised.
Yeah the warpage aspect is one of the most cited reasons for using copper pour, the other one is to prevent EMI but people who say this usually don't know why/how that works (or doesn't work). On some RF boards where we have copper pour placed for coplanar waveguide routing, I will have the fabricator review it because that copper distribution will almost always be uneven.
BTW, u need copper pour also cuz it evens up copper balance on PWB, preventing it from twisting. ALSO Copper pour is good heat sink and heat reflector for assembly (PWB could be twisted during soldering is it has been heated uneven). Also it is not bad to use pour as return path for slow signals ( not best idea, but from time to time u have no choice left)
Thermal is a good point, what's interesting is there is one older guy everyone knows who will say heatsinking and thermal transport is a myth, but then he turns around and says it interferes with assembly by removing heat from a solder joint! LOL.... For copper balance I've been told by a large manufacturer (they are my client) who runs millions of boards per year that it only matters on large boards, but it depends on material systems also. I guess that's one of those things where you can just ask if it's needed.
Hi Zack! Simply got impressed about the content and the way of presentation. Got bunch of ideas about via fencing. Thank you so much. Could you please make a video on HDI and back drill technology? It would be much helpful for new designers.
Hi Zack could you cover how to layout analog signals in a mixed signal layout where the analog frequency is below 20kHz. I have seen in a video from Rick Hartley talking about 20H separation where H is the height to the ground reference plane. But that more for analog signals above 20kHz. What is the way to avoid ground splits and separate the analog signals from digital portions
At audio frequencies, you need to avoid crosstalk from coupled fields and also avoid voltage drops due to the ground return being shared with noisy currents. Separate noisy digital circuits according to how their fields propagate. Use separate ground returns for sensitive analogue signals.
@@MattNeighbour Do you mean I should dedicate a plane for only routing analog signals referring ground planes on both sides? Or route the analog return as traces back to the ADC ground pin?
@@krisjk999 At the very least, keep the digital circuits separated from the analogue ones so the ground returns or fields don't mix. Many times one ground plane is best, but not always. It will be OK if there is xy distance between analogue and digital. Distance depends on bandwidth of digital agressor signals. If ADC is your focus it might be best to treat analogue ground like a differential pair with the analogue signal and route them together as traces to the ADC. Nothing on the PCB is a transmission line at 20kHz.
Nice explanation.....When a digital signal (which is a fundamental and odd harmonics) is used (rather than RF) what harmonic would you recommend designing the fence for? (9th, 11th ?)
Hey Zach! I am a systems design engineer on the hardware side and I had a question. One of the compelling arguments for copper pours, by Rick Hartley specifically, is the use of copper pours for manufacturing to reduce the amount of copper they have to scrape off. If filling copper everywhere is minimally good and sometimes bad from an EMI POV, do you think that it could generally be good to use for manufacturing simplicity and just know the times when copper pours are bad?
I'll just put it like this: when going back and forth with a vendor to get PCBs at quantity, I have never had a vendor suggest that I keep copper pour everywhere to reduce fab costs. And this includes the EMS companies I work with to get client projects into volume production, I see how they cost it and they have never brought this up. Maybe some companies price it like this and if they are doing any kind of etchant reclamation I would not be surprised, also maybe it was more common in the past. The only time I have had a suggestion from a manufacturer to keep pour is to prevent warpage on a large PCB because the copper is being used to balance the rigidity and heat distribution in the layer stackup during processing.
Nice video.....Can you please tell me how can I flow 60amps from my PCB? Can u please tell me about the copper thickness and trace width for that design
Hi Rohit, thanks for watching! For that high current, you will most likely need to do multiple planes that are interleaved. We've done backplanes that have to support over 100 A of current at different levels and it always ended up being done with multiple plane layers interleaved with ground layers. Those designs are also on physically thicker layer stacks, meaning multiple mm thick. Those are also higher layer count boards with 18-24 layers. For lower layer count it can be tricky because your board might be physically thinner/smaller and you have fewer layers. Without seeing specific design, I would only be able to say go with heavier copper and consider multiple power plane layers to support all of your current, but it also depends on the size of the board.
This has been asked so many times that I should now do a video on it. Just because a grounded conductor forms a circular shape does not mean it is a ground loop.
Hi zach, thank you very much for the video! , what about "S" distance between vías for stitching for a signal that can use diferent frequency in the same track, for example a cellular module antenna track, you can transmit data at diferent frequencies. What would be the ecuation?
If you're referring to a modulated analog signal, then you should use the carrier frequency. If you suppress the lowest order resonance for the carrier frequency (which will be a high frequency signal), then you'll also suppress all lower frequencies, which includes the modulating frequency and its harmonics.
@@Zachariah-Peterson hello sir, lower freq components in a signal have a bigger magnitude than high freq components So I'm confused because you say that suppressing the lower order resonance for the carrier freq will suppress all lower frequencies. By the way, if you have a PCB design course, how can I enroll? is the content is recorded videos or live sessions?
One question regarding the spacing between two vias in a viafancing. Do we not have to considere the bantwith of the Signal wich Eric bogation says depends Not on the frequency of the Signal but on the rise time? Bw = 0.35/tr
The rise time and frequency are related, meaning the rise time will determine the frequency content. Eric Bogatin is referring to a digital signal, which technically has infinite bandwidth, we just cut off the bandwidth somewhere to make analysis easier. The 0.35/tr value is the minimum bandwidth needed to measure a signal using an oscilloscope with a lowest order front-end filter, so it's an okay measure of bandwidth for most 1st order linear systems (which includes transmission lines, via fencing, etc.). So basically what this means is that you could still excite some higher order resonance in the via fencing structure, it just might be at high frequency and with low power, so you might not notice it in a real application.
This depends on the requried hole-to-hole wall spacing as determined by fabrication capabilities. This could be as low as 8 or 10 mils. I've placed below 10 mils in the past and then been asked to change it by the fabrication house, so make sure you check this. It also depends on the cost, if you want to spend less then use a larger drill size, but you might run into a problem with the hole-to-hole wall spacing, if that spacing is too small then you might have to reduce the via diameter.
Copper pour also minimizes the amount of etching. If you have large planes of copper to etch away it is probably worse for the environment. Also copper balancing is usually easier if layers are filled with copper, and finally usually it has a positive effect on thermal spreading. So my default would be copper pouring and then look how to handle the RF effects (maybe by selectively not pouring)
You can also apply selective clearances to specific objects or nets if the copper pour is not needed/wanted. For example with RF, if you are doing microstrips instead of coplanar waveguides you can always spread out the copper from an RF trace as needed, it does not have to run right up to the clearance limit. Clearly there are lots of decisions to balance here.
So i was in a discussion with another designer who stated that it is better to use power tracks over the board to supply power to components rather than using internal planes. eg like one giant plane for 3.3V and a seperate plane for GND ( i am in favor of the planes method) but he argued that it was better because you could route the power traces away from possible agressors to keep it clean. also you could add precise filtering on that power supply i have design a lot of boards only using internal planes and not just filling top and bottom with copper with great succes. b we are talking 6 layer boards, and nothing remotely highspeed ..so nothing fancy here, but with my understanding and playing around with PDN analysers it seems counter intuative to have a long "relatively thick" trace running on the your board to supply power. but i am curious on what your take would be on this. would love to prove the other guy wrong, but if not then i learned something new..
Well TBH, both approaches work fine in different situations. It's all about the goal you're trying to achieve. Motherboards and add-in cards that carry high speed signals use the SIG/GND/PWR/SIG type of arrangement and they have for years, and it's obviously successful. We've done boards running at WiFi and higher frequencies on SIG+PWR/GND/GND/SIG+PWR, although we never did PWR as copper pour. I can remember one design where that would make sense in hindsight. If you're running at low speeds but have dense components, maybe the plane is better because it will be easier to access power directly through a via, whereas a rail might have trouble getting to all your components. If you're designing something where there are really tight z-axis clearances that limit placement, you might be able to do it with rails, so a plane would make more sense. Maybe you have high current at multiple power levels (like above 20 A total), and on a 6 layer board that might mean you have maximum reliability with at least 1 power plane... again it all depends. Thick traces (100-200 mil wide) can handle a lot of current, planes can handle a lot more and still stay cool. Also if you're worried about inducing noise into a PWR plane, something like HS-SIG/GND/PWR/LS-SIG+GND will handle that just as well as routed power.
If you were to fill every bit of free space with vias you would create a near-solid wall of copper and the shielding effectiveness would be maintained up to very high frequencies/small wavelengths. Unfortunately, you can't actually do that with standard PCB processing due to resolution limits on etching and hole-to-hole clearance limits on drilling. So you can't just fill every space with vias in a practical situation.
Hey man, there seems to be a contradiction. I was watching this video from PCB Africa of a board review with Dan Beeker ua-cam.com/video/9-KG032lv8A/v-deo.html and he suggests to fill the top layer of the board, where power and signal tracks are, with GND pour. Then if you go to minute 5:25 you'll see that he is suggesting to separate the signal traces to allow the GND pour to flow in between them to improve signal integrity and EMI. That seems contradictory. Or doesn't it? I mean, could it be that what Dan is saying applies for low to medium speed microcontroller boards and what you say apply for high speed and RF boards? Or is there indeed a contradiction?
No I don't see a contradiction. We're all kind of talking past each other on this. Eric Bogatin's simulation result is consistent with Dan's reasoning. Eric's result show that adding in the copper pour with appropriately spaced out traces and appropriately spaced stitching, you would see a big crosstalk reduction of at least 30%. However, the crosstalk was already small to begin with, so if your goal was to reduce crosstalk then you might not have needed the copper pour. If crosstalk was probably low enough already, then why bother? Eric's conclusion would then be "if you have no other compelling reason for it, then don't use copper fill". Eric's conclusion of "it doesn't matter so why bother" is just as correct as Dan's conclusion of "it adds just that little bit of extra shielding, so if you do it right it won't hurt". My point is that, you'll get the most benefit if you design the pour/stitching appropriately, and Eric's simulation and Dan are consistent with that. I notice a lot that Eric stresses simplicity. I know he deals with a lot of college students, so my guess is he just wants them to really think about why they should add copper pour and focus more on the fundamentals (routing, stackup, grounding) instead of trying to band-aid their EMI problems with copper pour, which is totally appropriate and I think is the right way to train students. I think Dan could communicate the context a little better, but he's also correct about the shielding benefits of properly designed copper pour. So where do we all overlap? Here's where I think we can all agree: if you have some sort of EMI problem in the board that originates with stackup/grounding/routing, then you probably won't be successful trying to solve it by just adding copper fill to a bad board all over the signal/power layer. The corollary to that is, filling everything in with copper fill most likely won't cause your board to fail either as long as you've done all the other stuff correctly. The only instance where you've screwed up a good board is in two cases: 1) you leave the pour floating (no one does this anyways) and 2) you accidentally create a resonant cavity for your propagating signal, which is easily eliminated with stitching vias. At some point, the copper pour does provide more shielding (John Burkhert, Dan, and myself agree on this), which is always nice, but maybe you don't always need it.
@@Zachariah-Peterson awesome! Actually you metioned this in the video, I just forgot when I was watching Dan's video. Anyway thank you so much for the clarification, I really appreciate it!! And as for the GND copper pour, I used to do it but not anymore because I don't want to have to introduce like a million gnd stitching vias to avoid the resonances, especially since adding the pour doesn't help. But now I understand that better, so thanks again!
Can you show me how this can be used in a circuit with more than one trace? lol. Sorry. I just do not mentally visualize how this would work on a full PCB.
When you draw out the polygon it will automatically fill in the regions around traces while applying a clearance. I've shown other examples in videos where the pour is applied so that you can see what it would look like.
I would say at 7:30: not only inductive coupling, but also capacitive coupling is here present in manner of "displacement currents" .
thanks for the response! I never thought about how the copper layer could act as a coupling path between signal traces but it makes a lot of sense!
It's been nearly 2 years I'm working on my free time on a TFT dashboard for an old motorcycle, and I have a lot of troubles dealing with EMI. This video is really helpful understanding how that works and how possibly solve it. Thanks for all these information 🙏
great job Zach!
nice to see that you are interactive with your audience, thanks a lot.
keep up good work
amazing video and high quality explanation for via stitching.
One of the benefits I hear for using copper pour is to reduce the amount of etching chemicals used during manufacture. My understanding is that the copper layer is applied as a foil sheet to the full board surface and then etched away. Obviously it's important that the copper pour can't significantly affect signal integrity so it's really only applicable to slow-speed circuits?
Copper pour does matter at intermediate layer thicknesses where the parasitic capacitance to the pour is comparable to the capacitance to ground. That part of it matters more for high-speed circuits that are not on really thin layers, and the distance from the pour to the trace that you can tolerate depends on the impedance deviation you can accept. To solve that, just design the trace as if you were always going to use the pour anyways and then use thinner dielectric in the signal layers. For the etching part of it, you would have to get specific cost differences from a manufacturer. It is true that less of the etchant is needed when pour is included, but this could be insignificant to the overall cost when you get to high volume. Also, I have never had one of my manufacturers tell me that I can reduce cost if I just included the copper pour!
@@Zachariah-Peterson Thanks for the advice, good to know!
Zach You are the best, the videos are very usefull!! Greatings from argentina
5:55 it absolutely true, "If copper pour is not necessary, why do all the PCBs I see use copper pour on both the top and bottom? I don't understand at all. Even in your reviews."
At the time of doing this video I had not done a lot of instruction on the difference between 2 layer and 4 layer PCBs, but the distinction is relevant here. In a 2 layer PCB, copper pour is sometimes the only way to provide enough ground to provide return currents for digital signals, especially if you have double sided placement. If you see the copper pour in an assembled PCB, it might just be a 2 layer PCB. Once the component placement and routing density get high enough, it is not enough to apply ground with copper pour, so the easiest strategy is to use 4 layers with internal ground planes. In that instance, the copper pour is probably not needed as long as the outer layer is thin enough. These other issues with coupling across a region of copper pour is similar to what you would see with guard traces, the difference is that a copper pour region is just a wide guard trace.
I don't know, Zach, but I found that thumbnail to this video hilarious... Hat's off to the person who made it... You like some kind of Tribal Chief 😄
As always learning a lot from these videos. Thank You.
I recommend that the wavelength calculation should be corrected for effective dielectric constant of the medium of propagation: air + dielectric in the case of Microstrip or GCPW, or dielectric for Stripline. In the above example, 3GHz wavelength in FR4 would be closer to 40mm then the 100mm calculated assuming vacuum dielectric.
As far as the use of Dk-eff for wavelengths and stitching via spacing determination, that calculation would only be valid in the vicinity of the trace (when the trace is on the surface layer) where the transmission line appears coplanar. However, waves traveling into the dielectric or originating in the dielectric would only consider the value of the dielectric.
The other thing to think about here is the fact that the wavelength will be longer when Dk-eff is used compared to just Dk because Dk-eff < Dk. So as a result, if you size the stitching based on Dk, it will also provide the same shielding effectiveness in the region around a microstrip. The wavelength difference is only about 20% to 30%.
Thank you, Dr. Peterson.
Great video as usual and great thumbnail by the way.
Awesome!! Very nice and clear explanation about the via stitching and gnd copper pour everywhere. And yeah, almost everything in PCB Design comes down to proper stack-up and traces spacing.
Like your movies. Gr from The Netherlands
What is DKeff? 16:58
Meanwhile me having no clue what Im doing just filling up all the empty space on the top layer with pours and vias cause it looks cool
It does look cool LOL
11:24 Is this only effective for stripline? Or both stripline and microstrip.
The effectiveness for stripline and microstrip varies, we are essentially creating a large guard trace when doing this. In general for microstrip, getting an effective reduction requires to tie the copper to ground at each end of the interconnect, which is why you will see the stitching vias used as it will ensure this. For the stripline case you can watch this video to see the level of change by looking at near-end and far-end crosstalk: ua-cam.com/video/K1ob42Pv74Y/v-deo.html
I want to add one point from a assembly and production point of view. Not so much from the electric side. Having multiple layers, including the TOP and BOT with evenly distributed copper layers on it can be kinda helpful to counter PCB warping, specially on bigger layouts. Of course this does not help at all if the signal integrity is compromised.
Yeah the warpage aspect is one of the most cited reasons for using copper pour, the other one is to prevent EMI but people who say this usually don't know why/how that works (or doesn't work). On some RF boards where we have copper pour placed for coplanar waveguide routing, I will have the fabricator review it because that copper distribution will almost always be uneven.
BTW, u need copper pour also cuz it evens up copper balance on PWB, preventing it from twisting. ALSO Copper pour is good heat sink and heat reflector for assembly (PWB could be twisted during soldering is it has been heated uneven). Also it is not bad to use pour as return path for slow signals ( not best idea, but from time to time u have no choice left)
Thermal is a good point, what's interesting is there is one older guy everyone knows who will say heatsinking and thermal transport is a myth, but then he turns around and says it interferes with assembly by removing heat from a solder joint! LOL.... For copper balance I've been told by a large manufacturer (they are my client) who runs millions of boards per year that it only matters on large boards, but it depends on material systems also. I guess that's one of those things where you can just ask if it's needed.
Hi Zack! Simply got impressed about the content and the way of presentation. Got bunch of ideas about via fencing. Thank you so much.
Could you please make a video on HDI and back drill technology? It would be much helpful for new designers.
Hi Aravind, this is the 2nd question I received so far about backdrilling so it looks like I'll have to fast track it!
A really rare Case but in space electronics ground pour can be used as radiation shielding. We want as much Cooper as possible on all layers
hi zak where can i take your course
Hi Zack could you cover how to layout analog signals in a mixed signal layout where the analog frequency is below 20kHz. I have seen in a video from Rick Hartley talking about 20H separation where H is the height to the ground reference plane. But that more for analog signals above 20kHz. What is the way to avoid ground splits and separate the analog signals from digital portions
At audio frequencies, you need to avoid crosstalk from coupled fields and also avoid voltage drops due to the ground return being shared with noisy currents. Separate noisy digital circuits according to how their fields propagate. Use separate ground returns for sensitive analogue signals.
@@MattNeighbour Do you mean I should dedicate a plane for only routing analog signals referring ground planes on both sides? Or route the analog return as traces back to the ADC ground pin?
@@krisjk999 At the very least, keep the digital circuits separated from the analogue ones so the ground returns or fields don't mix. Many times one ground plane is best, but not always. It will be OK if there is xy distance between analogue and digital. Distance depends on bandwidth of digital agressor signals.
If ADC is your focus it might be best to treat analogue ground like a differential pair with the analogue signal and route them together as traces to the ADC. Nothing on the PCB is a transmission line at 20kHz.
Nice explanation.....When a digital signal (which is a fundamental and odd harmonics) is used (rather than RF) what harmonic would you recommend designing the fence for? (9th, 11th ?)
Fascinating
Could you also create something about trace, respectively shape current capability and what would be a appropriate value for T,
Is there any benefit of the copper shape itself? Seems like ALL of the benefit comes from the GND vias - not the GND shape?
Not necessarily, the benefit is from the span across the board and the vias.
Like to do pours where possible primarily to reduce copper etching as much as practical, helping out pcb fabricator in reducing waste.
Hey Zach! I am a systems design engineer on the hardware side and I had a question.
One of the compelling arguments for copper pours, by Rick Hartley specifically, is the use of copper pours for manufacturing to reduce the amount of copper they have to scrape off.
If filling copper everywhere is minimally good and sometimes bad from an EMI POV, do you think that it could generally be good to use for manufacturing simplicity and just know the times when copper pours are bad?
I'll just put it like this: when going back and forth with a vendor to get PCBs at quantity, I have never had a vendor suggest that I keep copper pour everywhere to reduce fab costs. And this includes the EMS companies I work with to get client projects into volume production, I see how they cost it and they have never brought this up. Maybe some companies price it like this and if they are doing any kind of etchant reclamation I would not be surprised, also maybe it was more common in the past. The only time I have had a suggestion from a manufacturer to keep pour is to prevent warpage on a large PCB because the copper is being used to balance the rigidity and heat distribution in the layer stackup during processing.
@@Zachariah-Petersonthey probably get the copper back in the process...
Nice video.....Can you please tell me how can I flow 60amps from my PCB? Can u please tell me about the copper thickness and trace width for that design
Hi Rohit, thanks for watching! For that high current, you will most likely need to do multiple planes that are interleaved. We've done backplanes that have to support over 100 A of current at different levels and it always ended up being done with multiple plane layers interleaved with ground layers. Those designs are also on physically thicker layer stacks, meaning multiple mm thick. Those are also higher layer count boards with 18-24 layers. For lower layer count it can be tricky because your board might be physically thinner/smaller and you have fewer layers. Without seeing specific design, I would only be able to say go with heavier copper and consider multiple power plane layers to support all of your current, but it also depends on the size of the board.
@@Zachariah-Petersonjust leave out solder mask and add solder to the heavy current tracks
Connecting ground pours together using vias at several places (far away from each other) would cause ground loops? Am I correct
This has been asked so many times that I should now do a video on it. Just because a grounded conductor forms a circular shape does not mean it is a ground loop.
Hi zach, thank you very much for the video! , what about "S" distance between vías for stitching for a signal that can use diferent frequency in the same track, for example a cellular module antenna track, you can transmit data at diferent frequencies. What would be the ecuation?
In that instance you would do the calculation for the highest frequency that will be present on the signal line.
If you're referring to a modulated analog signal, then you should use the carrier frequency. If you suppress the lowest order resonance for the carrier frequency (which will be a high frequency signal), then you'll also suppress all lower frequencies, which includes the modulating frequency and its harmonics.
@@joncedarleaf Thank you Jon!
@@Zachariah-Peterson thank you zach! I got it
@@Zachariah-Peterson hello sir,
lower freq components in a signal have a bigger magnitude than high freq components
So I'm confused because you say that suppressing the lower order resonance for the carrier freq will suppress all lower frequencies.
By the way, if you have a PCB design course, how can I enroll?
is the content is recorded videos or live sessions?
One question regarding the spacing between two vias in a viafancing.
Do we not have to considere the bantwith of the Signal wich Eric bogation says depends Not on the frequency of the Signal but on the rise time? Bw = 0.35/tr
The rise time and frequency are related, meaning the rise time will determine the frequency content. Eric Bogatin is referring to a digital signal, which technically has infinite bandwidth, we just cut off the bandwidth somewhere to make analysis easier. The 0.35/tr value is the minimum bandwidth needed to measure a signal using an oscilloscope with a lowest order front-end filter, so it's an okay measure of bandwidth for most 1st order linear systems (which includes transmission lines, via fencing, etc.).
So basically what this means is that you could still excite some higher order resonance in the via fencing structure, it just might be at high frequency and with low power, so you might not notice it in a real application.
what about the size (diameter) of the via ? how big or small should i make it ?
This depends on the requried hole-to-hole wall spacing as determined by fabrication capabilities. This could be as low as 8 or 10 mils. I've placed below 10 mils in the past and then been asked to change it by the fabrication house, so make sure you check this. It also depends on the cost, if you want to spend less then use a larger drill size, but you might run into a problem with the hole-to-hole wall spacing, if that spacing is too small then you might have to reduce the via diameter.
How do I separate 2 ground planes with signal transfer
Write to the e mail
So, what the answer? Pour or not? Why pour polygons topic ended up in crosstalk and shielding vias?
Because in engineering,the answer is often " it depends"
In Software you'll have straight answer, not in engineering
Copper pour also minimizes the amount of etching. If you have large planes of copper to etch away it is probably worse for the environment.
Also copper balancing is usually easier if layers are filled with copper, and finally usually it has a positive effect on thermal spreading.
So my default would be copper pouring and then look how to handle the RF effects (maybe by selectively not pouring)
You can also apply selective clearances to specific objects or nets if the copper pour is not needed/wanted. For example with RF, if you are doing microstrips instead of coplanar waveguides you can always spread out the copper from an RF trace as needed, it does not have to run right up to the clearance limit. Clearly there are lots of decisions to balance here.
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So i was in a discussion with another designer who stated that it is better to use power tracks over the board to supply power to components rather than using internal planes. eg like one giant plane for 3.3V and a seperate plane for GND ( i am in favor of the planes method) but he argued that it was better because you could route the power traces away from possible agressors to keep it clean. also you could add precise filtering on that power supply i have design a lot of boards only using internal planes and not just filling top and bottom with copper with great succes. b we are talking 6 layer boards, and nothing remotely highspeed ..so nothing fancy here, but with my understanding and playing around with PDN analysers it seems counter intuative to have a long "relatively thick" trace running on the your board to supply power. but i am curious on what your take would be on this. would love to prove the other guy wrong, but if not then i learned something new..
Well TBH, both approaches work fine in different situations. It's all about the goal you're trying to achieve. Motherboards and add-in cards that carry high speed signals use the SIG/GND/PWR/SIG type of arrangement and they have for years, and it's obviously successful. We've done boards running at WiFi and higher frequencies on SIG+PWR/GND/GND/SIG+PWR, although we never did PWR as copper pour. I can remember one design where that would make sense in hindsight.
If you're running at low speeds but have dense components, maybe the plane is better because it will be easier to access power directly through a via, whereas a rail might have trouble getting to all your components. If you're designing something where there are really tight z-axis clearances that limit placement, you might be able to do it with rails, so a plane would make more sense. Maybe you have high current at multiple power levels (like above 20 A total), and on a 6 layer board that might mean you have maximum reliability with at least 1 power plane... again it all depends. Thick traces (100-200 mil wide) can handle a lot of current, planes can handle a lot more and still stay cool. Also if you're worried about inducing noise into a PWR plane, something like HS-SIG/GND/PWR/LS-SIG+GND will handle that just as well as routed power.
sooooooo, just fill every space with vias and the wavelength dosent matter?
If you were to fill every bit of free space with vias you would create a near-solid wall of copper and the shielding effectiveness would be maintained up to very high frequencies/small wavelengths. Unfortunately, you can't actually do that with standard PCB processing due to resolution limits on etching and hole-to-hole clearance limits on drilling. So you can't just fill every space with vias in a practical situation.
Hey man, there seems to be a contradiction. I was watching this video from PCB Africa of a board review with Dan Beeker ua-cam.com/video/9-KG032lv8A/v-deo.html and he suggests to fill the top layer of the board, where power and signal tracks are, with GND pour. Then if you go to minute 5:25 you'll see that he is suggesting to separate the signal traces to allow the GND pour to flow in between them to improve signal integrity and EMI.
That seems contradictory. Or doesn't it? I mean, could it be that what Dan is saying applies for low to medium speed microcontroller boards and what you say apply for high speed and RF boards? Or is there indeed a contradiction?
No I don't see a contradiction. We're all kind of talking past each other on this.
Eric Bogatin's simulation result is consistent with Dan's reasoning. Eric's result show that adding in the copper pour with appropriately spaced out traces and appropriately spaced stitching, you would see a big crosstalk reduction of at least 30%. However, the crosstalk was already small to begin with, so if your goal was to reduce crosstalk then you might not have needed the copper pour. If crosstalk was probably low enough already, then why bother? Eric's conclusion would then be "if you have no other compelling reason for it, then don't use copper fill". Eric's conclusion of "it doesn't matter so why bother" is just as correct as Dan's conclusion of "it adds just that little bit of extra shielding, so if you do it right it won't hurt".
My point is that, you'll get the most benefit if you design the pour/stitching appropriately, and Eric's simulation and Dan are consistent with that. I notice a lot that Eric stresses simplicity. I know he deals with a lot of college students, so my guess is he just wants them to really think about why they should add copper pour and focus more on the fundamentals (routing, stackup, grounding) instead of trying to band-aid their EMI problems with copper pour, which is totally appropriate and I think is the right way to train students. I think Dan could communicate the context a little better, but he's also correct about the shielding benefits of properly designed copper pour.
So where do we all overlap? Here's where I think we can all agree: if you have some sort of EMI problem in the board that originates with stackup/grounding/routing, then you probably won't be successful trying to solve it by just adding copper fill to a bad board all over the signal/power layer. The corollary to that is, filling everything in with copper fill most likely won't cause your board to fail either as long as you've done all the other stuff correctly. The only instance where you've screwed up a good board is in two cases: 1) you leave the pour floating (no one does this anyways) and 2) you accidentally create a resonant cavity for your propagating signal, which is easily eliminated with stitching vias.
At some point, the copper pour does provide more shielding (John Burkhert, Dan, and myself agree on this), which is always nice, but maybe you don't always need it.
@@Zachariah-Peterson awesome! Actually you metioned this in the video, I just forgot when I was watching Dan's video. Anyway thank you so much for the clarification, I really appreciate it!!
And as for the GND copper pour, I used to do it but not anymore because I don't want to have to introduce like a million gnd stitching vias to avoid the resonances, especially since adding the pour doesn't help. But now I understand that better, so thanks again!
Can you show me how this can be used in a circuit with more than one trace? lol. Sorry. I just do not mentally visualize how this would work on a full PCB.
When you draw out the polygon it will automatically fill in the regions around traces while applying a clearance. I've shown other examples in videos where the pour is applied so that you can see what it would look like.
And if you a hobbyist and etching your pcb-s at home, the solution will last longer, if you don't etch the unnecessary parts.
4:00. My fabricator cares only about cm² and complexity category. complex = 0.146€ per cm² + 12€ job fee. So I don't care for this point.