Thank you for the video. Just today I was talking with a coworker how elegant the capacitor pre-charge circuit is. First we thought that the gate capacitor should be between gate and source, but connecting it to ground is much more effective. We saw this in a LT IC, for example LTC7003.
Thanks. I was not aware of the solution shown in the LTC7003. They seem to have missed few point though😊See the predecessor video ua-cam.com/video/05QprDgrP6E/v-deo.html. More important details can be found in the PCIM paper to be available at IEEExplore.
Glad to see you talking about more linear operation stuff and the Spirito effect! I didn't know about the SOATherm thing in LTSpice, so that's great to know about.
very clever analog trick. thank you for sharing this knowledge. specifically the capacitor gate drive, current limiting cap. i might try this out. Thanks!
in my implementation of.. almost the circuit seen at 6:02 it takes a short while for the HS gate driver to come online after power-on, and during that time Vd has a chance to rise towards its nominal value without Cb being charged, i.e. Vds rises. i found a resistor in parallell with M kept Vds lowish before M started conducting by pre-precharging Cb, and it helped my SOA issues without causing other issues in my usage case. I will definitively change to a x7r Cc tho, thats genious! thank you for the tip!
thank you sir for this important lesson , can you please make an episode about short circuit protection methods for IGBT, and the difference between short circuit and overload behavior , best regards.
Thank you, professor! I supposed estimating the right RthetaJA is not an easy task. especially when need to take into account the PCB matirials, heat sink, thermal paste, etc. Maybe you can do a video about that.
There is something unclear about that SOA table: at what time base does it work? 1 Hz? 50% dity cycle? Asking since I am not sure for example : I have a 100us puse of 200A at 10V that is ok according to the SOA BUT when can I have the next pulse like that? Also isn't this SOA graph simply a power that can be dissipated graph adjusted for thermal inertia and some heat disipation ? If yes then I can reverse math the linear behaviour, is that correct? Also at 5:17 is M1 meant to run in linear mode, as a current limiting resistor ? Besides capacitor banks and supercap backups what other loads have a capacitor like behaviours ? Asking since I can t think of any other use case for this circuit. I was also thinking that if we add a FET that disconnects C2 then the circuit can be also used to maybe soft start some SMPS? may not be the best method .
The SOA data is for a single pulse. For repetitive pulses you can use LTspice simulation or work it out via the thermal impedance plots given in the datasheets. These are in fact the origin of the SOA curves, save the secondary breakdown. As for 5:17, yes, Thanks for conversation.
Professor, when the MOSFET is switching the voltage and current is changing, how can I decide which current and voltage to use in the SOA? NOW I'm using the peak current and the input voltage, do you have any suggestions?
Using the non linearity of the value of the ceramic capacitor is very clever. I'll use it in future projects. Thank you !
👍🙏😊
Thank you for the video. Just today I was talking with a coworker how elegant the capacitor pre-charge circuit is. First we thought that the gate capacitor should be between gate and source, but connecting it to ground is much more effective. We saw this in a LT IC, for example LTC7003.
Thanks. I was not aware of the solution shown in the LTC7003. They seem to have missed few point though😊See the predecessor video ua-cam.com/video/05QprDgrP6E/v-deo.html. More important details can be found in the PCIM paper to be available at IEEExplore.
Glad to see you talking about more linear operation stuff and the Spirito effect! I didn't know about the SOATherm thing in LTSpice, so that's great to know about.
👍🙏
It is new feature added less than year ago.
Very helpful, thank you very much.
Thanks
Glad to see this comprehensive video to explain SOA and linear operations.
Thanks for comment
very clever analog trick. thank you for sharing this knowledge. specifically the capacitor gate drive, current limiting cap. i might try this out. Thanks!
👍🙏
in my implementation of.. almost the circuit seen at 6:02 it takes a short while for the HS gate driver to come online after power-on, and during that time Vd has a chance to rise towards its nominal value without Cb being charged, i.e. Vds rises. i found a resistor in parallell with M kept Vds lowish before M started conducting by pre-precharging Cb, and it helped my SOA issues without causing other issues in my usage case. I will definitively change to a x7r Cc tho, thats genious! thank you for the tip!
👍Thanks for comment. Have you seen ua-cam.com/video/05QprDgrP6E/v-deo.html ?
@@sambenyaakov yes. i mentioned that i had built something similar, and asked where i could send schematic if you were interested
@@solenskinerable sby@irpsystems.com
@@solenskinerable sam.benyaakov@gmail.com
thank you sir for this important lesson , can you please make an episode about short circuit protection methods for IGBT, and the difference between short circuit and overload behavior , best regards.
God subject, will try to prepare a video on that. Thanks.
So, I have a doubt. If I connect this MOSFET to an DC channel which can have maximum 1A, so what will be the max Vds of this device ?
What is Vgs?
Thank you, professor! I supposed estimating the right RthetaJA is not an easy task. especially when need to take into account the PCB matirials, heat sink, thermal paste, etc. Maybe you can do a video about that.
Good subject. Will try.
There is something unclear about that SOA table: at what time base does it work? 1 Hz? 50% dity cycle?
Asking since I am not sure for example : I have a 100us puse of 200A at 10V that is ok according to the SOA BUT when can I have the next pulse like that?
Also isn't this SOA graph simply a power that can be dissipated graph adjusted for thermal inertia and some heat disipation ? If yes then I can reverse math the linear behaviour, is that correct?
Also at 5:17 is M1 meant to run in linear mode, as a current limiting resistor ?
Besides capacitor banks and supercap backups what other loads have a capacitor like behaviours ? Asking since I can t think of any other use case for this circuit.
I was also thinking that if we add a FET that disconnects C2 then the circuit can be also used to maybe soft start some SMPS? may not be the best method .
The SOA data is for a single pulse. For repetitive pulses you can use LTspice simulation or work it out via the thermal impedance plots given in the datasheets. These are in fact the origin of the SOA curves, save the secondary breakdown. As for 5:17, yes, Thanks for conversation.
Professor, when the MOSFET is switching the voltage and current is changing, how can I decide which current and voltage to use in the SOA? NOW I'm using the peak current and the input voltage, do you have any suggestions?
Run LTspice simulation
👍🙏❤
👍🙏😊