My favourite state machine, always blocks: one or many? and simplifying your SystemVerilog Style!

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  • Опубліковано 12 жов 2024

КОМЕНТАРІ • 13

  • @FPGAsforBeginners
    @FPGAsforBeginners  День тому +9

    Hi Everyone and thanks for checking out my new video! I'm really happy with this one! Phew! It has taken a month of prep and 3 recording attempts to get it exactly as I like it, but now I can happily say I've distilled my favourite state machine (and surrounding topics) into 30 min! Hope you enjoy!

  • @cccmmm1234
    @cccmmm1234 21 годину тому

    Everyone should have a favorite state machine!
    Thanks Stacey, educational as always.

  • @ignacioosorio7942
    @ignacioosorio7942 20 годин тому

    I'm so happy to have found this channel! Thanks for your content!

  • @jiteshnayak7338
    @jiteshnayak7338 2 години тому

    This video was so freaking good it was so clear and to the point thanks for this

  • @TahaAlars
    @TahaAlars День тому +3

    Amazing work as usual, thank u for the great effort 😊

  • @MrHeatification
    @MrHeatification День тому +2

    As a colleague engineer I love your content

  • @cccmmm1234
    @cccmmm1234 21 годину тому

    Almost 10k subs. Catching fire!

  • @hjvanderlinden
    @hjvanderlinden День тому +2

    Bedankt

  • @MuhammadAbdullah-n4w
    @MuhammadAbdullah-n4w День тому +3

    amazing videos

  • @productivemonk5261
    @productivemonk5261 4 години тому

    My favorite statemachine is synchronous and not pseudo synchronous like your statemachine. The synthesized result is mostly the same, but one extra clock cycle per state. It’s my preferred method.

  • @guest7329
    @guest7329 18 годин тому

    Great tutorial😊
    does state_counter consume more energy because of state transitions (for counter value itself) for states that don't use it?

  • @productivemonk5261
    @productivemonk5261 4 години тому

    Could be combined into one synchronous always block, don’t need three blocks.