Hold Time | STA | Back To Basics

Hold Time in VLSI | STA | Back To Basics
This video explains what is Hold Time, how is the equation of Hold time derived, what is hold time of a D-flip flop and why is hold time checked at the same edge?
Some of the other videos are given below:
D-Latch & D-Flip Flop
• D-Latch & D-Flip flop.
Set Up Time
• Set Up Time | STA | B...
Find all my videos on Physical Only Cells in the following playlist.
/ @backtobasics5602
Temperature Inversion
• Temperature Inversion ...
Working of MOSFET
• Working of a MOSFET
Antenna Effects
• Antenna Effects | Phys...
Outro Template : zipansion.com/1...
#Hold#VLSI #BackToBasics

[@abhijeetbhadre2018]

Your videos are very informative and they clears most of the doubts. Thank you.

[@kalpanaverma4340]

Your explanation is actually good
And very clear too
Thanks 🙏

[@blablabla12a]

Thank you very much. I finally understand this now.

[@mallikaputsala2354]

Great explanation, this video clears all my doubts..Thanku for posting this type of content

[@rupambanik5556]

Such beautifully explained!!

[@sandeepkumarravirala7028]

Excellent videos

[@Sowmya3699]

Wonderful explanation mam

[@Harshavardhan-yt3he]

This video cleared my doubt thanks

[@payaldas9086]

Very informative video!!

[@Agigeorge1984]

very good. Thank you

[@srujannama4676]

very clear explanation

[@pavankumarmvs6728]

excellent explanation

[@vinaykushwaha5223]

nice video !

[@shreyaovalekar6764]

Thank you!

[@manjumaldakal1598]

EXCELLENT

[@raghuvamsiyellampalli7415]

can you do video on input files and sanity checks of physical design in every stage

[@orugantimanideep2209]

So, if you have combinational circuit before the transmission gate, Thold should be Tcombo taken away from the time taken for transmission gate to turn off completely.
Thold = Ttrasnmission - Tcombo
Is it correct?

[@LakshmiNarayana-qk9zt]

Thank you

[@gopikrishnakakani]

Please do videos about Dynamic and Static Power Consumption and methods to reduce power..

[@backtobasics5602]

Sure.

[@successpage6866]

Thanks .ur video awasome

[@backtobasics5602]

:)

[@prashantsaxena2477]

Lovely video!
I had a request that can you make a video on Hold time analysis with multiple clocks . For example, what will be the hold time equation between a positively edge triggered launch flop and a negatively edge triggered capture flop. (both launch and capture flops having different clocks).
Or is there a video already on it?

[@surendralodhi8997]

Nice explanation mam

[@niroshaj.r.1730]

Please do videos on static and dynamic power dissipation

[@backtobasics5602]

Sure.

[@niroshaj.r.1730]

Thank you

[@rawjeev3476]

Required time= tperiod + hold time? Correct me if I'm wrong

[@movies3946]

So, Hold check will be done at capture flop , it has to check whether data is stable after clock has reached it, whatever data that is lanched by lanched flop , after it got captured by capture flop. it should not moves so faster that it can collide with next data , it has to stable for Libray Hold time of capture flop .................... can anyone correct me ??

[@akashlakhera3727]

it's a nice explaination. Can you please provide video on latch timing anaysis?

[@backtobasics5602]

Thanks.
Sure, will do a video on latch timing in future.

[@User--jm5911]

Why the hold check is same edge I can't undersood can You tell cleary once again if u don't mind

[@orugantimanideep2209]

You see,
presuming you understood why data launched at one edge is captured at the next edge,
If I change data input at first edge, it will be captured at the second edge. Now, from this video, you know what the hold time of DFF is. Let us say, I changed my input at the second edge of the clock. If the arriving time of this data is less than the hold time of the DFF, the present input(at the second edge of arrival clock) is potential enough to change the past input(second edge of the capture clock). The whole phenomenon takes place at the second edges of the arriving clock and capturing clock. Hope it's clear.