Kudos Zach and Altium Academy for this great piece. I would also like you touch base with instances you cannot avoid splits on high edge-rate signals. I use small caps near the split and the signals. Also about how good is edge ground region to prevent leaking at the edge.
Nicely explained. 6-layer is beyond the needs of anything I'd build, but this is interesting. tl;dw: Close coupling between the signal layers and ground; thicker core to reduce coupling between the internal signal layers. That solid power region in the hand-on example is essentially a shielding can. V0, V+, don't really make no nevermind - they're both ground as far as the signal is concerned. In fact, with faster edge rate signals, it can be beneficial to have coupling between both the V0 and V+ rails.
I'd put the PWR layer closest to the layer where the high speed components and their decoupling capacitors are mounted to minimise the loop inductance. ETA: I.e. if components on L1, GND on L2 and PWR on L3.
Zack, Would there be issues with having power layer 3 and signal on layer 4 in terms of coupling? I realize that you have ground on layer 5 for layer 4 to couple to, but I'm trying to parse what Rick Hartley is recommending vs. what you have here. He's basically saying to have: SIG/PWR GND SIG/PWR GND SIG/PWR GND
I know the Rick Hartley presentation you're referring to, the "never ever do it" case is microstrip over split PWR layer. With slower signals and coplanar ground you can get away with it. I'm doing it with striplines, having the splits on layer 3 is not ideal but we are a bit constrained by the stackup from the manufacturer (in this case, JLC as I discussed in a short). This one won't go through EMI testing so I'm not worried about the design in those terms, but if edge emissions were a problem it's simple to correct this by adding a GND layer between 3 and 4, or by making the dielectric between 3 and 4 thick while making the 4/5 and 2/3 dielectrics very thin.
Was this stackup (8:45) an in-progress draft, or were there some subtle choices that would be worth explaining? It looks like the thick center layer is "Dielectric", the ones near it are "core" and the outer ones are "prepreg". Is "dialectric" just a way to say the fabricator can choose? (It does list a specific Dk, different from either the core or prepreg, but that might be a default.) Is it common to use so many different materials? Is this for cost-savings, and more relevant at volume? The L3-Power layer is only half-ounce copper, even though all the other layers -- including its symmetric L4 -- are full-ounce. In the past, when I've seen an asymmetry, it was to _increase_ the thickness of a power plane. Was this a copper-balance concern, or something I haven't even considered?
You can have the thinner prepreg as the central dielectric, and then thicker cores around it. More common is to use the thicker core as central dielectric and 2 prepreg layers on top or on bottom. The stackup shown on the screen matched a standard JLC stackup that we used when I ordered the boards (you can see those boards in a short: ua-cam.com/users/shortsvxkrQup6H1I), you can see the stackup details on their 6-layer PCB stackup support page, that one ends up with 1/2 ounce on inner layers and 1 ounce on surface so ignore those values in the LSM. If you look at that stackup you'll see that they spec different glass weaves for the different layers, this stackup mostly has tight spread glass so it addresses fiber weave problems. So yes it is common to mix different materials like this, sometimes that's the only way to hit your thickness targets on different layers.
Altium has an SI tool that uses either BEM or MoM to do 2D impedance calculations from your PCB layout, and it can apply some terminations to examine reflections and ringing. You can also do some basic crosstalk simulations, and the tool is quite good for that purpose. There are no PI simulations directly from the PCB layout, you can only do things in SPICE or you have to use an integration with Keysight to do this. There is also an Ansys CoDesigner integration that can be used for SI and PI.
Hi, does having a reference layer close to the power plane make a big difference for decoupling ? With a 6 layer stackup as shown with one or two power plane layers in comparison with an basic 4 layer sig-gnd-pwr-sig stackup.
At 9:13 and 9:17, the vias seem to be labelled. Is that just a nice feature of the Altium User Interface, or is that silkscreen on tented vias? If it will show on the actual board, what made the vias more annotation-worthy than other pads?
Those are through-hole pads, and Altium (along with other ECAD software) will display the net names in the GUI. These aren't in silkscreen layers or anything like that.
@@Zachariah-Peterson , at JLCPCB uses just Through Hole vias. So, my question is regarded to how to connect GND planes, cause there are some vias related to some GND pins (like decouple caps and IC pins) and in this case do I need provide other vias (Stitching ones) to connect the GND planes ?
In the initial stackup with SIG on L3 and L4, the two ground planes are sharing the return currents with the same coupling on the layers above and below. In this case, how do we handle the crosstalk between L1 - L3 and L4 - L6 signals? Can orthogonal routing be used as a general solution to avoid crosstalk issues? And as always, thanks for the great video! @Zachariah-Peterson
There is not any crosstalk between L1-L3 and L4-L6 when there is GND on L2 and L5. Electromagnetic fields cannot penetrate through the GND plane at the frequencies of interest in digital PCBs by any appreciable amount due to the skin depth. Standard 1 oz. copper is ~6 skin depths thick at 100 GMz, and about 18 skin depths thick at 1 GHz. This is enough to block wave propagation through the copper foil. In general, orthogonal routing can be considered as a way to route signals so that they have minimal capacitive and inductive coupling, but it is only necessary when you don't have GND between signal layers.
Starting around 10:20, you discuss routing over splits in the power plane -- but I would expect coupling to the nearby ground plane to be 40-50 times stronger, so that power plane discontinuities couldn't approach the 5%-10% tolerance of controlled impedance. Are these signals particularly sensitive? Is the tolerance for controlled impedance _variation_ within a single board much tighter than the overall target?
At 11:48, when routing over splits in the power plane -- does serpentining within the split affect the timing skew? Is that typically modeled by the tools, or just something to watch out for and manually request a field-solving simulation there?
Due to the distance to ground being larger than power I don't know if 40-50x is the right number, but regardless there is coupling to GND so it will not be a major problem for impedance discontinuity. We showed in another video about S-parameters being affected by splits in power planes, those splits need to be pretty large to become noticeable in a return loss plot at lower frequencies (this should make perfect sense if you think about critical length). However, the Bert Simonovich article I reference in that video looks at emissions around those splits, which are noticeable at higher frequencies, so there is a risk if you do a lot of this. Also the serpentine timing is affected by a small amount, Altium Designer and every other CAD tool cannot account for this until after the route is completed and a 2D/3D simulation is run.
I was thinking about square of distance, forgetting that planes are just linear ... so if the actual factor is less than 10, I guess it could exceed the 10% tolerance.
I think you're referring to the length tuning applied to some of the traces, this is used to ensure the signals on a group of traces are synchronized so that they arrive at the receiving component at the same time.
When L3(Power) is used as a reference plane for L4(signal), even though the distance is "large", wont there be some field spreading as the field has to rely on decoupling capacitors as return path?
The majority of return current sits in the closer conductor, yes there could be some flow through nearby decaps but much less than you would expect through the nearby GND. At somewhat high speeds the current can pass over splits and you won't notice the effects on S-parameters until you get to very high frequencies. In my PCB West presentation from this year I showed some examples with small splits in a plane on a 100G serdes lane, and you get about -2 dB return loss degradation up to the 20-30 GHz range, much lower frequencies like we are dealing with here are mostly unaffected. There could be EMI if routing over a split in the power layer, but again it depends on the signal edge rate and how close the signal is to GND compared to power.
I assume that the cutout on the inner layer around the ddr traces was used necessary to achieve the target impedance. I would increase the cutout area to have the external traces (the one on top and the one on the bottom) not influenced by the pour.
@AlbertRei3424 I did not understand how the area of the cutout region on the internal layer that is away from external layers (especially from top layer) affects the signals on external layers
It's an easy way to apply ground clearance to all the signals in that region while maintaining GND everywhere else. We could increase the clearance rule to those nets as well, but there is a risk you get dead copper in that area and it's a big pain to fix.
Great video Zach. No doubt it will help a lot of newer designers.
I hope so, that's why we do this
Kudos Zach and Altium Academy for this great piece. I would also like you touch base with instances you cannot avoid splits on high edge-rate signals. I use small caps near the split and the signals. Also about how good is edge ground region to prevent leaking at the edge.
Nicely explained. 6-layer is beyond the needs of anything I'd build, but this is interesting.
tl;dw: Close coupling between the signal layers and ground; thicker core to reduce coupling between the internal signal layers.
That solid power region in the hand-on example is essentially a shielding can. V0, V+, don't really make no nevermind - they're both ground as far as the signal is concerned. In fact, with faster edge rate signals, it can be beneficial to have coupling between both the V0 and V+ rails.
I'd put the PWR layer closest to the layer where the high speed components and their decoupling capacitors are mounted to minimise the loop inductance. ETA: I.e. if components on L1, GND on L2 and PWR on L3.
Zack,
Would there be issues with having power layer 3 and signal on layer 4 in terms of coupling? I realize that you have ground on layer 5 for layer 4 to couple to, but I'm trying to parse what Rick Hartley is recommending vs. what you have here. He's basically saying to have:
SIG/PWR
GND
SIG/PWR
GND
SIG/PWR
GND
I know the Rick Hartley presentation you're referring to, the "never ever do it" case is microstrip over split PWR layer. With slower signals and coplanar ground you can get away with it. I'm doing it with striplines, having the splits on layer 3 is not ideal but we are a bit constrained by the stackup from the manufacturer (in this case, JLC as I discussed in a short). This one won't go through EMI testing so I'm not worried about the design in those terms, but if edge emissions were a problem it's simple to correct this by adding a GND layer between 3 and 4, or by making the dielectric between 3 and 4 thick while making the 4/5 and 2/3 dielectrics very thin.
Was this stackup (8:45) an in-progress draft, or were there some subtle choices that would be worth explaining?
It looks like the thick center layer is "Dielectric", the ones near it are "core" and the outer ones are "prepreg". Is "dialectric" just a way to say the fabricator can choose? (It does list a specific Dk, different from either the core or prepreg, but that might be a default.)
Is it common to use so many different materials? Is this for cost-savings, and more relevant at volume?
The L3-Power layer is only half-ounce copper, even though all the other layers -- including its symmetric L4 -- are full-ounce. In the past, when I've seen an asymmetry, it was to _increase_ the thickness of a power plane. Was this a copper-balance concern, or something I haven't even considered?
You can have the thinner prepreg as the central dielectric, and then thicker cores around it. More common is to use the thicker core as central dielectric and 2 prepreg layers on top or on bottom. The stackup shown on the screen matched a standard JLC stackup that we used when I ordered the boards (you can see those boards in a short: ua-cam.com/users/shortsvxkrQup6H1I), you can see the stackup details on their 6-layer PCB stackup support page, that one ends up with 1/2 ounce on inner layers and 1 ounce on surface so ignore those values in the LSM. If you look at that stackup you'll see that they spec different glass weaves for the different layers, this stackup mostly has tight spread glass so it addresses fiber weave problems. So yes it is common to mix different materials like this, sometimes that's the only way to hit your thickness targets on different layers.
Is it possible to perform SI & PI simulations by Altium? How did you analyze the board in terms of SI/PI?
Altium has an SI tool that uses either BEM or MoM to do 2D impedance calculations from your PCB layout, and it can apply some terminations to examine reflections and ringing. You can also do some basic crosstalk simulations, and the tool is quite good for that purpose. There are no PI simulations directly from the PCB layout, you can only do things in SPICE or you have to use an integration with Keysight to do this. There is also an Ansys CoDesigner integration that can be used for SI and PI.
Hi, does having a reference layer close to the power plane make a big difference for decoupling ? With a 6 layer stackup as shown with one or two power plane layers in comparison with an basic 4 layer sig-gnd-pwr-sig stackup.
At 9:13 and 9:17, the vias seem to be labelled. Is that just a nice feature of the Altium User Interface, or is that silkscreen on tented vias? If it will show on the actual board, what made the vias more annotation-worthy than other pads?
Those are through-hole pads, and Altium (along with other ECAD software) will display the net names in the GUI. These aren't in silkscreen layers or anything like that.
GND pouring on signal layer, will help to reduce the Radiation? If yes can you pls explain how its helping.
Regarding the vias and pads, mainly vias connected to GND and PWR, these vias are over all stackup ?
What does "over all stackup" mean?
@@Zachariah-Peterson , at JLCPCB uses just Through Hole vias. So, my question is regarded to how to connect GND planes, cause there are some vias related to some GND pins (like decouple caps and IC pins) and in this case do I need provide other vias (Stitching ones) to connect the GND planes ?
In the initial stackup with SIG on L3 and L4, the two ground planes are sharing the return currents with the same coupling on the layers above and below. In this case, how do we handle the crosstalk between L1 - L3 and L4 - L6 signals? Can orthogonal routing be used as a general solution to avoid crosstalk issues? And as always, thanks for the great video! @Zachariah-Peterson
There is not any crosstalk between L1-L3 and L4-L6 when there is GND on L2 and L5. Electromagnetic fields cannot penetrate through the GND plane at the frequencies of interest in digital PCBs by any appreciable amount due to the skin depth. Standard 1 oz. copper is ~6 skin depths thick at 100 GMz, and about 18 skin depths thick at 1 GHz. This is enough to block wave propagation through the copper foil. In general, orthogonal routing can be considered as a way to route signals so that they have minimal capacitive and inductive coupling, but it is only necessary when you don't have GND between signal layers.
Hi Zach
Can you explain why impedance discontinuity and mismatch creates radiation and EMI problems
Starting around 10:20, you discuss routing over splits in the power plane -- but I would expect coupling to the nearby ground plane to be 40-50 times stronger, so that power plane discontinuities couldn't approach the 5%-10% tolerance of controlled impedance.
Are these signals particularly sensitive? Is the tolerance for controlled impedance _variation_ within a single board much tighter than the overall target?
At 11:48, when routing over splits in the power plane -- does serpentining within the split affect the timing skew? Is that typically modeled by the tools, or just something to watch out for and manually request a field-solving simulation there?
Due to the distance to ground being larger than power I don't know if 40-50x is the right number, but regardless there is coupling to GND so it will not be a major problem for impedance discontinuity. We showed in another video about S-parameters being affected by splits in power planes, those splits need to be pretty large to become noticeable in a return loss plot at lower frequencies (this should make perfect sense if you think about critical length). However, the Bert Simonovich article I reference in that video looks at emissions around those splits, which are noticeable at higher frequencies, so there is a risk if you do a lot of this. Also the serpentine timing is affected by a small amount, Altium Designer and every other CAD tool cannot account for this until after the route is completed and a 2D/3D simulation is run.
I was thinking about square of distance, forgetting that planes are just linear ... so if the actual factor is less than 10, I guess it could exceed the 10% tolerance.
I don't know if it's a dumb question, but why are there some trails that take multiple turns and intentional longer paths?
I think you're referring to the length tuning applied to some of the traces, this is used to ensure the signals on a group of traces are synchronized so that they arrive at the receiving component at the same time.
I assume those internal layer 4 routing of the DDR signals referencing to that power plane (L3) have the same potential.
When L3(Power) is used as a reference plane for L4(signal), even though the distance is "large", wont there be some field spreading as the field has to rely on decoupling capacitors as return path?
The majority of return current sits in the closer conductor, yes there could be some flow through nearby decaps but much less than you would expect through the nearby GND. At somewhat high speeds the current can pass over splits and you won't notice the effects on S-parameters until you get to very high frequencies. In my PCB West presentation from this year I showed some examples with small splits in a plane on a 100G serdes lane, and you get about -2 dB return loss degradation up to the 20-30 GHz range, much lower frequencies like we are dealing with here are mostly unaffected. There could be EMI if routing over a split in the power layer, but again it depends on the signal edge rate and how close the signal is to GND compared to power.
I assume that the cutout on the inner layer around the ddr traces was used necessary to achieve the target impedance.
I would increase the cutout area to have the external traces (the one on top and the one on the bottom) not influenced by the pour.
Good eye, after filming we put the board through fabrication and we did provide some larger margin to that polygon cutout border.
@@Zachariah-Peterson I assume we are talking about the cutout 10:28 on layer 4. How are the cutout influencing the traces on the top and bottom layer?
@AlbertRei3424 I did not understand how the area of the cutout region on the internal layer that is away from external layers (especially from top layer) affects the signals on external layers
@@burakkahraman5438 He is referring to the traces near the edge of the cutout, not external layers
Why apply a void around the ddr signals
It's an easy way to apply ground clearance to all the signals in that region while maintaining GND everywhere else. We could increase the clearance rule to those nets as well, but there is a risk you get dead copper in that area and it's a big pain to fix.
Nice
Привет, Зак.