DVCon Europe 2021 - Sessions P3.1, P3.2, P3.3

Presented at DVCon Europe 2021
This video consists of three presentations.
-- Bringing Reset Domains and Power Domains Together - Set/Reset Flops Augmenting Complexities in Power-Aware RDC Verification
By Manjunatha Srinivas¹; Manish Bhati¹; Abdul Moyeen¹; Inayat Ali²
¹ Siemens Digital Industries Software; ² NXP Semiconductors
-- A Methodology for Evaluating SI Artefacts in DDR4-3DS PHY using Channel Modelling
By Aditya S Kumar; Gowdra Bomanna Chethan; Shivani Maurya; Anil Deshpande; Somasunder Kattepura Sreenath Samsung Semiconductor India R & D Centre(SSIR)
-- Using Dependency Injection Design Pattern in Power Aware Tests
By Mehmet Tukel¹; Luca Sasselli; David Guthrie ¹ QUALCOMM Ireland
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