In the day 9 question, shouldn't the answer be option (c), because x + 0 = x. x is don't care, means it can be 0 or 1 so if we add 0/1 to 0 it will be 0/1. So, in this way the closest answer should be 4'b110x
We didn't define ports in Top module and there is no ; semicolon in module instantiation and C_in will be wire because it is input and we take input using wire not reg I don't know it is correct or not so please reply
Can you explain why the carry in (cin) in the first adder can be left unconnected? When I did this, I explicitly connected it to 1’b0. If seems like it would be ‘x’ if you didn’t connect it to anything. 🤔
Yes always better to connect to 0 as otherwise it might take z or x (i need to see) so to have a deterministic behaviour it’s advisable to connect it to 0
This guy is really a gem. 💙From NIT Silchar
In the day 9 question, shouldn't the answer be option (c), because x + 0 = x. x is don't care, means it can be 0 or 1 so if we add 0/1 to 0 it will be 0/1. So, in this way the closest answer should be 4'b110x
You ligic seems perfect , let me see why i thought of a different answer
We didn't define ports in Top module and there is no ; semicolon in module instantiation and C_in will be wire because it is input and we take input using wire not reg
I don't know it is correct or not so please reply
There is no connection between the top and the inner module since the port of the inner module and top modules are left unconnected.
Can you explain why the carry in (cin) in the first adder can be left unconnected? When I did this, I explicitly connected it to 1’b0. If seems like it would be ‘x’ if you didn’t connect it to anything. 🤔
Yes always better to connect to 0 as otherwise it might take z or x (i need to see) so to have a deterministic behaviour it’s advisable to connect it to 0
@@whyRD Thank you for the reply and the great series. I’m learning and enjoying every second!
Sir,when will the layout project next video will come
I am trying my best to bring it ASAP , please allow me some time , i know its already late and any time i get some time shoot that video , dont worry
@@whyRD Thank you sir
bhaiya I'am having problem while using iverilog with vscode , can u plz create one Short video?
In recent days not possible, as i am fully occupied with this series and project series…. Please try to get some other resources
ok thank u
@@whyRD
sir how did we get output here without concatenating both the sum at the end ??
Partial selection of vectors, add1's sum is assigned to the first 16 bits and add2 to the last 16 bits, the output port is 32 bits
Sir , how should I get 5 bit(from A to Z alphabet and each has 5 bit )range encoding in verilog code